-- =======================================================================
-- Author:  Antonio Esteves, GEC-DI-UM.
-- File:    ur_add8.vhd
-- Date:    13 August 2000
--
-- Non-Loadable w-bit Registered Unsigned Adder.
-- Targeted into XC4xxx family.
--  
-- Functionality:
--                 s[w:0] = a[w-1:0] + b[w-1:0] + ci
--
-- =======================================================================

library IEEE;
use     IEEE.STD_LOGIC_1164.all;

ENTITY unsigned_r_add IS

   generic (w: NATURAL);

   PORT(
                               -- value 1 to be added: (w-1 DOWNTO 0)
      a       : IN  std_logic_vector(w-1 DOWNTO 0); 
                               -- value 2 to be added: (w-1 DOWNTO 0)
      b       : IN  std_logic_vector(w-1 DOWNTO 0);
      c       : IN  std_logic; -- clock of result register
      ce      : IN  std_logic; -- clock enable of result register
      ci      : IN  std_logic; -- input carry
      clr     : IN  std_logic; -- clear of result register
                               -- result of addition: (w DOWNTO 0)
      s       : OUT std_logic_vector(w DOWNTO 0)
      );
END    unsigned_r_add;

ARCHITECTURE behaviour OF unsigned_r_add IS

   signal    res : std_logic_vector( w DOWNTO 0 ) ;

   FUNCTION plus
      (
      a, b  : std_logic_vector;
      cin   : std_logic;
      width : integer
      ) RETURN std_logic_vector IS

      VARIABLE retval : std_logic_vector(width-1 DOWNTO 0);
      VARIABLE carry  : std_logic_vector(width DOWNTO 0);

   BEGIN

      carry(0) := cin;
      FOR i IN 0 TO width-1 LOOP
         retval(i)  := a(i) XOR b(i) XOR carry(i);
         carry(i+1) := (a(i) AND b(i)) or (a(i) AND carry(i)) or
                       (b(i) AND carry(i));
      END LOOP;
      RETURN retval;
   END plus;

BEGIN

   process (c, clr)

      variable a_ext : std_logic_vector( w DOWNTO 0 ) ;
      variable b_ext : std_logic_vector( w DOWNTO 0 ) ;
  
   begin

      a_ext(a'high downto a'low) := a;
      a_ext(w) := '0';
      b_ext(b'high downto b'low) := b;
      b_ext(w) := '0';

      if (clr = '1') then
         res <= (OTHERS => '0');
      elsif (c'event and c = '1') then
         if (ce = '1') then
            res <= plus(a_ext, b_ext, ci, w+1);
         end if;
      end if; 
   end process;

   s  <=  res;

end behaviour;