-- =======================================================================
-- Author:  Antonio Esteves, GEC-DI-UM.
-- File:    s_r_sub.vhd
-- Date:    13 August 2000
--
-- Non-Loadable w-bit Registered Signed Subtracter
-- Targeted into XC4xxx family.
--
-- Functionality:
--                 r[w:0] = a[w-1:0] - b[w-1:0] - bi
--
--                 bi = 1 (exists borrow), 0 (no borrow)
--  
-- =======================================================================

library IEEE;
use     IEEE.STD_LOGIC_1164.all;

entity signed_r_sub is
   generic (
      w: NATURAL
      );
   port (
                               -- value to subtract from: (w-1 DOWNTO 0)
      a       : IN  std_logic_vector(w-1 downto 0);
                               -- value to be subtracted: (w-1 DOWNTO 0)
      b       : IN  std_logic_vector(w-1 downto 0);
      clk     : IN  std_logic; -- clock of result register
      ce      : IN  std_logic; -- clock enable of result register
      bi      : IN  std_logic; -- input borrow
      reset   : IN  std_logic; -- clear of result register
                               -- result of subtraction: (w DOWNTO 0)
      r       : OUT std_logic_vector(w downto 0)
      );
end signed_r_sub;

ARCHITECTURE behv OF signed_r_sub IS

   signal dif : std_logic_vector(w DOWNTO 0) ;

   FUNCTION minus (
      a     : std_logic_vector;
      b     : std_logic_vector;
      bin   : std_logic;
      width : integer
      )
      RETURN std_logic_vector IS
      
   VARIABLE retval : std_logic_vector(width-1 DOWNTO 0);
   VARIABLE borrow : std_logic;

   BEGIN
      borrow := not(bin);
      FOR i IN 0 TO width-1 LOOP
         retval(i) := a(i) XOR NOT(b(i)) XOR borrow;
         borrow    := (a(i) AND (NOT b(i)))  OR 
                   (a(i) AND  borrow) OR 
                   ((NOT b(i)) AND borrow);
      END LOOP;
      RETURN retval;
   END minus;    

BEGIN

   process (clk, reset)

      variable a_ext : std_logic_vector(w DOWNTO 0) ;
      variable b_ext : std_logic_vector(w DOWNTO 0) ;

   begin
      a_ext(a'high downto a'low) := a;
      a_ext(w) := a(a'high);
      b_ext(b'high downto b'low) := b;
      b_ext(w) := b(b'high);

      if (reset = '1') then
         dif <= (OTHERS => '0');
      elsif (clk'event and clk = '1') then
         if (ce = '1') then
            dif <= minus(a_ext, b_ext, bi, w+1);
         end if;
      end if; 
   end process;

   r <= dif;
   
end behv;