-- =======================================================================
-- Author:  Antonio Esteves, GEC-DI-UM.
-- File:    ram80x16.vhd
-- Date:    13 August 2000
--
-- RAM with 80 positions by 16-bit defined using xilinx RAM32X1S 
-- and RAM16X1S components.
-- =======================================================================

library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.std_logic_unsigned.all;

entity ram_80x16 is
   port (
      d              : in  std_logic_vector(15 downto 0); -- input data
      add_rd         : in  std_logic_vector( 6 downto 0); -- read address
      add_wr         : in  std_logic_vector( 6 downto 0); -- write address
      clk            : in  std_logic;                     -- write clock
      we             : in  std_logic;                     -- write enable
      written3l      : in  std_logic;                     -- used to select read/write address
      conv1line_done : in  std_logic;                     -- used to select read/write address
      not_oe_lsb     : in  std_logic;                     -- output enable to read LSByte
      not_oe_msb     : in  std_logic;                     -- output enable to read MSByte
      o              : out std_logic_vector ( 7 downto 0) -- output data
      );
end ram_80x16;

architecture struct_xilinx of ram_80x16 is

   component RAM32X1S
      generic (init_val: string := "00000000");
      port (
         D    : in  std_logic;
         WE   : in  std_logic;
         WCLK : in  std_logic;
         A0   : in  std_ulogic;
         A1   : in  std_ulogic;
         A2   : in  std_ulogic;
         A3   : in  std_ulogic;
         A4   : in  std_logic;
         O    : out std_logic
         );
   end component;

   component RAM16X1S
      generic (init_val: string := "0000");
      port (
         D    : in  std_ulogic;
         WE   : in  std_ulogic;
         WCLK : in  std_ulogic;
         A0   : in  std_ulogic;
         A1   : in  std_ulogic;
         A2   : in  std_ulogic;
         A3   : in  std_ulogic;
         O    : out std_ulogic
         );
   end component;

   signal out_00, out_01, out_10, out_mux : std_logic_vector (d'range);
   signal we_00, we_01, we_10 : std_logic;
   signal add     : std_logic_vector (add_rd'range);
   signal sel_add : std_logic;
 
begin

   -- signal to select between read and write address -------------------

   sel_add <= written3l and (not conv1line_done);

   -- Write Enable's for the 3 RAM parts --------------------------------

   we_00 <= we and (not add(6)) and (not add(5));
   we_01 <= we and (not add(6)) and add(5);
   we_10 <= we and add(6) and (not add(5)) and (not add(4));

   -- selector between read and write address (7 x mux2:1 ) -------------

   MUXES_ADD: for n in add_rd'range generate
      process (sel_add, add_rd(n), add_wr(n))
      begin
         if (sel_add='0') then
            add(n) <= add_rd(n) ;
         else
            add(n) <= add_wr(n) ;
         end if;
      end process;
   end generate MUXES_ADD;

   -- selector between the output of the 3 RAM parts (16 x mux4:1) ------

   MUXES_O: for n in d'range generate
      process (add(6), add(5), out_00(n),  out_01(n), out_10(n))
      begin
         if    (add(6)='0' and add(5)='0') then
            out_mux(n) <= out_00(n) ;
         elsif (add(6)='0' and add(5)='1') then
            out_mux(n) <= out_01(n) ;
         elsif (add(6)='1' and add(5)='0') then
            out_mux(n) <= out_10(n) ;
         else
            out_mux(n) <= '0';
         end if;
      end process;
   end generate MUXES_O;

   -- multiplex the 16-bit out RAM into 8 bits, to be read via PCI bus

   READ_15_8:
      process(not_oe_msb, out_mux)
      begin
         if (not_oe_msb = '0') then 
            o  <= out_mux (15 downto 8) ;
         else 
            o <= "ZZZZZZZZ" ;
         end if ;
      end process;

   READ_7_0:
      process(not_oe_lsb, out_mux)
      begin
         if (not_oe_lsb = '0') then 
            o  <= out_mux (7 downto 0) ;
         else 
            o <= "ZZZZZZZZ" ;
         end if ;
      end process;

   -- RAM modules with least significant 32 positions [31:0] of 1-bit ---

   RAMS_00: for n in d'range generate
      U00: RAM32X1S generic map ("00000000")
      port map (
         D    => d(n)      ,
         WE   => we_00     ,
         WCLK => clk       ,
         A0   => add(0)    ,
         A1   => add(1)    ,
         A2   => add(2)    ,
         A3   => add(3)    ,
         A4   => add(4)    ,
         O    => out_00(n) 
         );
   end generate RAMS_00;

   -- RAM modules with positions [63:32] of 1-bit -----------------------

   RAMS_01: for n in d'range generate
      U01: RAM32X1S generic map ("00000000")
      port map (
         D    => d(n)      ,
         WE   => we_01     ,
         WCLK => clk       ,
         A0   => add(0)    ,
         A1   => add(1)    ,
         A2   => add(2)    ,
         A3   => add(3)    ,
         A4   => add(4)    ,
         O    => out_01(n) 
         );
   end generate RAMS_01;

   -- RAM modules with positions [79:64] of 1-bit -----------------------

   RAMS_10: for n in d'range generate
      U10: RAM16X1S generic map ("0000")
      port map (
         D    => d(n)      ,
         WE   => we_10     ,
         WCLK => clk       ,
         A0   => add(0)    ,
         A1   => add(1)    ,
         A2   => add(2)    ,
         A3   => add(3)    ,
         O    => out_10(n) 
         );
   end generate RAMS_10;

end struct_xilinx;

-- =======================================================================