-- ======================================================================= -- Author: Antonio Esteves, GEC-DI-UM. -- File: ram208x8.vhd -- Date: 09 August 2000 -- -- RAM with 208 positions by 8-bit defined using xilinx RAM32X1S -- and RAM16X1S components. -- ======================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ram_208x8 is port ( d : in std_logic_vector ( 7 downto 0); -- input data add_rd : in std_logic_vector ( 7 downto 0); -- read address add_wr : in std_logic_vector ( 7 downto 0); -- write address clk : in std_logic; -- write clock we : in std_logic; -- write enable sel_add : in std_logic; -- selector of read/write address o : out std_logic_vector ( 7 downto 0) -- output data ); end ram_208x8; architecture struct_xilinx of ram_208x8 is component RAM32X1S generic (init_val: string := "00000000"); port ( D : in std_logic; WE : in std_logic; WCLK : in std_logic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_logic; O : out std_logic ); end component; component RAM16X1S generic (init_val: string := "0000"); port ( D : in std_ulogic; WE : in std_ulogic; WCLK : in std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; O : out std_ulogic ); end component; signal out_000, out_001, out_010, out_011, out_100, out_101, out_110, out_mux : std_logic_vector (d'range); signal we_000, we_001, we_010, we_011, we_100, we_101, we_110 : std_logic; signal add : std_logic_vector (add_rd'range); begin -- Write Enable's for the 7 RAM parts -------------------------------- we_000 <= we and (not add(7)) and (not add(6)) and (not add(5)) ; we_001 <= we and (not add(7)) and (not add(6)) and add(5) ; we_010 <= we and (not add(7)) and add(6) and (not add(5)) ; we_011 <= we and (not add(7)) and add(6) and add(5) ; we_100 <= we and add(7) and (not add(6)) and (not add(5)) ; we_101 <= we and add(7) and (not add(6)) and add(5) ; we_110 <= we and add(7) and add(6) and (not add(5)) and (not add(4)); -- selector between read and write address (8 x mux2:1 ) ------------- MUXES_ADD: for n in add_rd'range generate process (sel_add, add_rd(n), add_wr(n)) begin if (sel_add='0') then add(n) <= add_wr(n) ; else add(n) <= add_rd(n) ; end if; end process; end generate MUXES_ADD; -- selector between the output of the 7 RAM parts (8 x mux8:1) ------ MUXES_O: for n in o'range generate process (add(7), add(6), add(5), out_000(n), out_001(n), out_010(n), out_011(n), out_100(n), out_101(n), out_110(n)) begin if (add(7)='0' and add(6)='0' and add(5)='0') then o(n) <= out_000(n) ; elsif (add(7)='0' and add(6)='0' and add(5)='1') then o(n) <= out_001(n) ; elsif (add(7)='0' and add(6)='1' and add(5)='0') then o(n) <= out_010(n) ; elsif (add(7)='0' and add(6)='1' and add(5)='1') then o(n) <= out_011(n) ; elsif (add(7)='1' and add(6)='0' and add(5)='0') then o(n) <= out_100(n) ; elsif (add(7)='1' and add(6)='0' and add(5)='1') then o(n) <= out_101(n) ; elsif (add(7)='1' and add(6)='1' and add(5)='0') then o(n) <= out_110(n) ; else o(n) <= '0'; end if; end process; end generate MUXES_O; -- RAM modules with least significant 32 positions [31:0] of 1-bit --- RAMS_000: for n in d'range generate U000: RAM32X1S generic map ("00000000") port map ( D => d(n) , WE => we_000 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , A4 => add(4) , O => out_000(n) ); end generate RAMS_000; -- RAM modules with positions [63:32] of 1-bit ----------------------- RAMS_001: for n in d'range generate U001: RAM32X1S generic map ("00000000") port map ( D => d(n) , WE => we_001 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , A4 => add(4) , O => out_001(n) ); end generate RAMS_001; -- RAM modules with positions [95:64] of 1-bit ----------------------- RAMS_010: for n in d'range generate U010: RAM32X1S generic map ("00000000") port map ( D => d(n) , WE => we_010 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , A4 => add(4) , O => out_010(n) ); end generate RAMS_010; -- RAM modules with positions [127:96] of 1-bit ---------------------- RAMS_011: for n in d'range generate U011: RAM32X1S generic map ("00000000") port map ( D => d(n) , WE => we_011 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , A4 => add(4) , O => out_011(n) ); end generate RAMS_011; -- RAM modules with positions [128:159] of 1-bit --------------------- RAMS_100: for n in d'range generate U100: RAM32X1S generic map ("00000000") port map ( D => d(n) , WE => we_100 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , A4 => add(4) , O => out_100(n) ); end generate RAMS_100; -- RAM modules with positions [160:191] of 1-bit --------------------- RAMS_101: for n in d'range generate U101: RAM32X1S generic map ("00000000") port map ( D => d(n) , WE => we_101 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , A4 => add(4) , O => out_101(n) ); end generate RAMS_101; -- RAM modules with positions [207:192] of 1-bit --------------------- RAMS_110: for n in d'range generate U110: RAM16X1S generic map ("0000") port map ( D => d(n) , WE => we_110 , WCLK => clk , A0 => add(0) , A1 => add(1) , A2 => add(2) , A3 => add(3) , O => out_110(n) ); end generate RAMS_110; end struct_xilinx; -- ========================================================================