-- ======================================================================= -- Author: Antonio Esteves, GEC-DI-UM. -- File: proc_convol.vhd -- Date: 15 August 2000 -- -- Component allocated to FPGAs 1:4 for the hw/sw convolution -- implementation. -- Synthesizable version. -- ======================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_arith.all; use WORK.functions_util.all; -- ======================================================================= -- lines_in: RAM onde o s/w guarda 'maskY' parcelas (de 'maskY' linhas -- diferentes) de tamanho 'colunas' da imagem original, a -- usar em cada FPGA e em cada iteracao da convolucao. -- line_out: sinal onde a FPGA guarda uma parcela de linha (de tamanho -- 'colunas') da imagem convoluida, obtida em cada iteracao -- do algoritmo de convolucao por cada FPGA. -- tx: numero de colunas da imagem original -- ty: numero de linhas da imagem original -- masc: mascara (guardada numa ROM) a aplicar na imagem -- maskX: numero de colunas da mascara a aplicar (= 3) -- maskY: numero de linhas da mascara a aplicar (= 3) -- max: valor maximo da parcela de imagem convoluida pela FPGA (nao -- normalizada). -- min: valor minimo da parcela de imagem convoluida pela FPGA (nao -- normalizada). -- read_done: indica que o s/w terminou a leitura (a partir dum ficheiro) -- da imagem a processar. -- write_done: indica que o s/w terminou a escrita (em ficheiro) da imagem -- convoluida. -- convol_done: 4 semaforos que indicam se cada uma das 4 FPGAs ja'terminou -- a convolucao da parcela de imagem que lhe foi alocada. -- conv1line_done: 4 semaforos que indicam se cada uma das 4 parcelas -- pertencentes 'a mesma linha foram convoluidas por cada uma -- das FPGAs; quando activos indicam que o seu armazenamento -- na imagem convoluida (tarefa executada pelo s/w) pode -- iniciar-se. -- wr_finished: semaforo activado pelo s/w para indicar 'as FPGAs que uma -- linha convoluida foi escrita na imagem de saida; deste modo -- a convolucao de uma nova linha pode comecar. -- written3l: semaforo que permite ao s/w sinalizar 'as FPGAs que ja' tem -- disponiveis 'maskY' novas parcelas para serem convoluidas. -- accept3l: 4 semaforos que indicam que cada uma das 4 FPGAs esta'pronta -- para aceitar 'maskY' novas parcelas de linha para convoluir. -- start_fsm: sinal que permite ao s/w indicar 'as FPGAs que a convolucao -- de uma nova imagem se vai iniciar. -- ======================================================================= entity processa_convol is PORT ( NOTWR : in std_logic ; NOTRD : in std_logic ; RESET : in std_logic ; PCLOCK : in std_logic ; SCLOCK : in std_logic ; BASE_HIT0 : in std_logic ; ADDR_VLD : in std_logic ; S_DATA_VLD : in std_logic ; PCI_CMD7 : in std_logic ; PCI_CMD6 : in std_logic ; S_CBE : in std_logic ; ADDR : in std_logic_vector(17 downto 0) ; DATA : inout std_logic_vector( 7 downto 0) ; S_SRC_EN : in std_logic ; S_DATA : in std_logic ; DATA_UP : inout std_logic_vector(32 downto 0) ; DATA_DWN : inout std_logic_vector(32 downto 0) ; CONNECTOR : inout std_logic_vector(15 downto 0) ; DATA2CPLD : inout std_logic_vector( 7 downto 0) ; CLK_CPLD : in std_logic_vector( 1 downto 0) ; CLK_DWN_OUT : out std_logic ; CLK_DWN_IN : in std_logic ; CLK_UP_OUT : out std_logic ; CLK_UP_IN : in std_logic ; GENERICO : inout std_logic_vector( 2 downto 1) ) ; end processa_convol; ARCHITECTURE structural OF processa_convol IS component fpga_interface port ( -- signals connecting the FPGA to the exterior NOTWR : in std_logic ; NOTRD : in std_logic ; RESET : in std_logic ; PCLOCK : in std_logic ; SCLOCK : in std_logic ; BASE_HIT0 : in std_logic ; ADDR_VLD : in std_logic ; S_DATA_VLD : in std_logic ; PCI_CMD7 : in std_logic ; PCI_CMD6 : in std_logic ; S_CBE : in std_logic ; ADDR : in std_logic_vector(17 downto 0) ; DATA : inout std_logic_vector( 7 downto 0) ; S_SRC_EN : in std_logic ; S_DATA : in std_logic ; DATA_UP : inout std_logic_vector(32 downto 0) ; DATA_DWN : inout std_logic_vector(32 downto 0) ; CONNECTOR : inout std_logic_vector(15 downto 0) ; DATA2CPLD : inout std_logic_vector( 7 downto 0) ; CLK_CPLD : in std_logic_vector( 1 downto 0) ; CLK_DWN_OUT : out std_logic ; CLK_DWN_IN : in std_logic ; CLK_UP_OUT : out std_logic ; CLK_UP_IN : in std_logic ; GENERICO : inout std_logic_vector( 2 downto 1); -- signals connecting to the rest of the FPGA logic NOTWR_I : out std_logic ; NOTRD_I : out std_logic ; RESET_I : out std_logic ; PCLOCK_I : out std_logic ; SCLOCK_I : out std_logic ; BASE_HIT0_I : out std_logic ; ADDR_VLD_I : out std_logic ; S_DATA_VLD_I : out std_logic ; PCI_CMD7_I : out std_logic ; PCI_CMD6_I : out std_logic ; S_CBE_I : out std_logic ; ADDR_I : out std_logic_vector(17 downto 0) ; DATA_I : out std_logic_vector( 7 downto 0) ; DATA_O : in std_logic_vector( 7 downto 0) ; S_SRC_EN_I : out std_logic ; S_DATA_I : out std_logic ; DATA_UP_O : in std_logic_vector(32 downto 0) ; DATA_UP_I : out std_logic_vector(32 downto 0) ; CONNECTOR_O : in std_logic_vector(15 downto 0) ; CONNECTOR_I : out std_logic_vector(15 downto 0) ; DATA_DWN_O : in std_logic_vector(32 downto 0) ; DATA_DWN_I : out std_logic_vector(32 downto 0) ; DATA2CPLD_O : in std_logic_vector( 7 downto 0) ; DATA2CPLD_I : out std_logic_vector( 7 downto 0) ; CLK_CPLD_I : out std_logic_vector( 1 downto 0) ; CLK_DWN_OUT_O : in std_logic ; CLK_DWN_IN_I : out std_logic ; CLK_UP_OUT_O : in std_logic ; CLK_UP_IN_I : out std_logic ; GENERICO_O : in std_logic_vector( 2 downto 1) ; GENERICO_I : out std_logic_vector( 2 downto 1) ; -- signals to control tri-state buffers on bi-direccional pins not_oe_d : in std_logic; not_oe_d2c : in std_logic; not_oe_dup : in std_logic; not_oe_ddwn : in std_logic; not_oe_gen : in std_logic; not_oe_conn : in std_logic ); end component ; component ctl_fpga_interface port ( NOTWR_I : in std_logic ; NOTRD_I : in std_logic ; RESET_I : in std_logic ; PCLOCK_I : in std_logic ; BASE_HIT0_I : in std_logic ; ADDR_VLD_I : in std_logic ; S_DATA_VLD_I : in std_logic ; PCI_CMD7_I : in std_logic ; PCI_CMD6_I : in std_logic ; ADDR_I : in std_logic_vector(17 downto 0) ; S_DATA_I : in std_logic ; not_oe_line_outL : out std_logic; not_oe_line_outM : out std_logic; not_oe_maxL : out std_logic; not_oe_maxM : out std_logic; not_oe_minL : out std_logic; not_oe_minM : out std_logic; not_oe_accept3l : out std_logic; not_oe_conv1line_done : out std_logic; not_oe_convol_done : out std_logic; load_lines_in : out STD_LOGIC; load_read_done : out STD_LOGIC; load_write_done : out STD_LOGIC; load_written3l : out STD_LOGIC; load_wr_finished : out STD_LOGIC; load_start_fsm : out STD_LOGIC; load_reset_ff : out STD_LOGIC ); end component; component fsm is port ( clk : in STD_LOGIC; reset_ff : in STD_LOGIC; start_fsm : in STD_LOGIC; read_done : in STD_LOGIC; write_done : in STD_LOGIC; written3l : in STD_LOGIC; wr_finished : in STD_LOGIC; counting_l : in STD_LOGIC; counting_c : in STD_LOGIC; counting_ml : in STD_LOGIC; counting_mc : in STD_LOGIC; rst_a3l : out STD_LOGIC; rst_cdone_max_min : out STD_LOGIC; rst_cdonel : out STD_LOGIC; rst_1ptcontrib : out STD_LOGIC; set_cdone : out STD_LOGIC; set_a3l : out STD_LOGIC; set_cdonel : out STD_LOGIC; load_line : out STD_LOGIC; load_column : out STD_LOGIC; load_mline : out STD_LOGIC; load_mcolumn : out STD_LOGIC; clk_line : out STD_LOGIC; clk_column : out STD_LOGIC; clk_mline : out STD_LOGIC; clk_mcolumn : out STD_LOGIC; we_store1pt : out STD_LOGIC; ce_s1_m1_m2 : out STD_LOGIC; ce_a1_a2 : out STD_LOGIC; ce_add3 : out STD_LOGIC; ce_mult3 : out STD_LOGIC; ce_add4 : out STD_LOGIC; ce_1ptcontrib : out STD_LOGIC ); end component; component unsigned_r_add is generic (w: NATURAL); PORT ( a : IN std_logic_vector(w-1 DOWNTO 0); b : IN std_logic_vector(w-1 DOWNTO 0); c : IN std_logic; ce : IN std_logic; ci : IN std_logic; clr : IN std_logic; s : OUT std_logic_vector(w DOWNTO 0) ); end component; component sign_r_add is generic (w: NATURAL); PORT ( a : IN std_logic_vector(w-1 DOWNTO 0); b : IN std_logic_vector(w-1 DOWNTO 0); c : IN std_logic; ce : IN std_logic; ci : IN std_logic; clr : IN std_logic; s : OUT std_logic_vector(w DOWNTO 0) ); end component; component unsigned_r_sub is generic (w: NATURAL); PORT ( a : IN std_logic_vector(w-1 DOWNTO 0); b : IN std_logic_vector(w-1 DOWNTO 0); c : IN std_logic; ce : IN std_logic; bi : IN std_logic; clr : IN std_logic; r : OUT std_logic_vector(w DOWNTO 0) ); end component; component unsigned_mult is generic ( aw: NATURAL; bw: NATURAL ); port ( a : in std_logic_vector(aw-1 downto 0); b : in std_logic_vector(bw-1 downto 0); c : in std_logic; ce : in std_logic; reset : in std_logic; prod : out std_logic_vector(aw+bw-1 downto 0) ); end component; component signed_mult is generic ( aw: NATURAL; bw: NATURAL ); port ( a : in std_logic_vector(aw-1 downto 0); b : in std_logic_vector(bw-1 downto 0); c : in std_logic; ce : in std_logic; reset : in std_logic; prod : out std_logic_vector(aw+bw-1 downto 0) ); end component; component counterDownToValue is generic (w: NATURAL); port ( start : in std_logic_vector(w-1 downto 0); stop : in std_logic_vector(w-1 downto 0); c : in std_logic; load : in std_logic; reset : in std_logic; count : inout std_logic_vector(w-1 downto 0); counting : inout std_logic ) ; end component; component counterDown is generic (w: NATURAL); port ( start : in std_logic_vector (w-1 downto 0); c : in std_logic; load : in std_logic; reset : in std_logic; count : inout std_logic_vector (w-1 downto 0); counting : inout std_logic ); end component; component ram_80x16 is port ( d : in std_logic_vector (15 downto 0); add_rd : in std_logic_vector ( 6 downto 0); add_wr : in std_logic_vector ( 6 downto 0); clk : in std_logic; we : in std_logic; written3l : in std_logic; conv1line_done : in std_logic; not_oe_lsb : in std_logic; not_oe_msb : in std_logic; o : out std_logic_vector ( 7 downto 0) ); end component; component ram_208x8 is port ( d : in std_logic_vector ( 7 downto 0); add_rd : in std_logic_vector ( 7 downto 0); add_wr : in std_logic_vector ( 7 downto 0); clk : in std_logic; we : in std_logic; sel_add : in std_logic; o : out std_logic_vector ( 7 downto 0) ); end component; -- ROM 16 x 6-bit generated with LOGIBLOX (rom16x6.ngc file) component rom16x6 port ( A : in std_logic_vector(3 downto 0); DO : out std_logic_vector(5 downto 0) ); end component; component ffd_ce is port ( data_in : in std_logic; clock : in std_logic; enable : in std_logic; data_out : out std_logic ); end component; component ffd_ce_rst is port ( data_in : in std_logic; clock : in std_logic; enable : in std_logic; reset : in std_logic; data_out : out std_logic ); end component; component ffd_rst_syncset is port ( data_in : in std_logic; clock : in std_logic; reset : in std_logic; set : in std_logic; data_out : out std_logic ); end component; component signed_r_sub is generic ( w: NATURAL ); port ( a : IN std_logic_vector(w-1 downto 0); b : IN std_logic_vector(w-1 downto 0); clk : IN std_logic; ce : IN std_logic; bi : IN std_logic; reset : IN std_logic; r : OUT std_logic_vector(w downto 0) ); end component; -- -------------------------------------------------------------- -- signals connecting the FPGA PADs to the rest of the FPGA logic -- -------------------------------------------------------------- signal NOTWR_I : std_logic ; signal NOTRD_I : std_logic ; signal RESET_I : std_logic ; signal PCLOCK_I : std_logic ; signal SCLOCK_I : std_logic ; signal BASE_HIT0_I : std_logic ; signal ADDR_VLD_I : std_logic ; signal S_DATA_VLD_I : std_logic ; signal PCI_CMD7_I : std_logic ; signal PCI_CMD6_I : std_logic ; signal S_CBE_I : std_logic ; signal ADDR_I : std_logic_vector(17 downto 0) ; signal DATA_I : std_logic_vector( 7 downto 0) ; signal DATA_O : std_logic_vector( 7 downto 0) ; signal S_SRC_EN_I : std_logic ; signal S_DATA_I : std_logic ; signal DATA_UP_O : std_logic_vector(32 downto 0) ; -- NOT USED signal DATA_UP_I : std_logic_vector(32 downto 0) ; -- NOT USED signal CONNECTOR_O : std_logic_vector(15 downto 0) ; -- NOT USED signal CONNECTOR_I : std_logic_vector(15 downto 0) ; -- NOT USED signal DATA_DWN_O : std_logic_vector(32 downto 0) ; -- NOT USED signal DATA_DWN_I : std_logic_vector(32 downto 0) ; -- NOT USED signal DATA2CPLD_O : std_logic_vector( 7 downto 0) ; -- NOT USED signal DATA2CPLD_I : std_logic_vector( 7 downto 0) ; -- NOT USED signal CLK_CPLD_I : std_logic_vector( 1 downto 0) ; -- NOT USED signal CLK_DWN_OUT_O : std_logic ; -- NOT USED signal CLK_DWN_IN_I : std_logic ; -- NOT USED signal CLK_UP_OUT_O : std_logic ; -- NOT USED signal CLK_UP_IN_I : std_logic ; -- NOT USED signal GENERICO_O : std_logic_vector( 2 downto 1) ; -- NOT USED signal GENERICO_I : std_logic_vector( 2 downto 1) ; -- NOT USED -- ----------------------------------------------------------- -- signals to control tri-state buffers on bi-direccional pads -- ----------------------------------------------------------- signal not_oe_d : std_logic; signal not_oe_d2c : std_logic; -- NOT USED signal not_oe_dup : std_logic; -- NOT USED signal not_oe_ddwn : std_logic; -- NOT USED signal not_oe_gen : std_logic; -- NOT USED signal not_oe_conn : std_logic; -- NOT USED -- ---------------------------------------------------------- -- Convolution algorithm signals -- ---------------------------------------------------------- signal maskY : std_logic_vector(1 downto 0); -- mask lines signal maskX : std_logic_vector(1 downto 0); -- mask columns signal ty : std_logic_vector(8 downto 0); -- image lines signal tx : std_logic_vector(8 downto 0); -- image columns -- half maskX dimension signal a : std_logic_vector(6 downto 0); -- number of columns to be processed by FPGA signal colunas : std_logic_vector(6 downto 0); -- line counter output signal line : std_logic_vector(7 downto 0); -- line counter is not stopped signal counting_l : std_logic; -- start value for line counter signal start_line : std_logic_vector(8 downto 0); -- column counter output signal column : std_logic_vector(6 downto 0); -- column counter is not stopped signal counting_c : std_logic; -- start value for column counter signal start_column : std_logic_vector(6 downto 0); -- mask line counter output signal mline : std_logic_vector(1 downto 0); -- mask line counter is not stopped signal counting_ml : std_logic; -- start value for mask line counter signal start_mline : std_logic_vector(1 downto 0); -- mask column counter output signal mcolumn : std_logic_vector(6 downto 0); -- mask column counter is not stopped signal counting_mc : std_logic; -- start value for mask column counter signal start_mcolumn : std_logic_vector(6 downto 0); -- clock for all the system signal clk : std_logic; -- reset for all the system signal reset_ff : std_logic; -- maximum convolved value signal max : std_logic_vector(15 downto 0); -- 'max' register clock enable signal ce_max : std_logic; signal update_max : std_logic; -- minimum convolved value signal min : std_logic_vector(15 downto 0); -- 'min' register clock enable signal ce_min : std_logic; signal update_min : std_logic; signal convol_done : STD_LOGIC; signal conv1line_done : STD_LOGIC; signal accept3l : STD_LOGIC; signal read_done : STD_LOGIC; signal write_done : STD_LOGIC; signal written3l : STD_LOGIC; signal wr_finished : STD_LOGIC; signal start_fsm : STD_LOGIC; signal rst_cdone_ored, rst_cdonel_ored, rst_a3l_ored : std_logic; signal sig_gnd, sig_vcc : std_logic; -- -------------------------------------------------------------- -- FSM outputs -- -------------------------------------------------------------- signal rst_a3l : STD_LOGIC; signal rst_cdone_max_min : STD_LOGIC; signal rst_cdonel : STD_LOGIC; signal rst_1ptcontrib : STD_LOGIC; signal set_cdone : STD_LOGIC; signal set_a3l : STD_LOGIC; signal set_cdonel : STD_LOGIC; signal load_line : STD_LOGIC; signal load_column : STD_LOGIC; signal load_mline : STD_LOGIC; signal load_mcolumn : STD_LOGIC; signal clk_line : STD_LOGIC; signal clk_column : STD_LOGIC; signal clk_mline : STD_LOGIC; signal clk_mcolumn : STD_LOGIC; signal we_store1pt : STD_LOGIC; signal ce_s1_m1_m2 : STD_LOGIC; signal ce_a1_a2 : STD_LOGIC; signal ce_add3 : STD_LOGIC; signal ce_mult3 : STD_LOGIC; signal ce_add4 : STD_LOGIC; signal ce_1ptcontrib : STD_LOGIC; -- -------------------------------------------------------------- -- Signals used to compute each convolved pixel -- -------------------------------------------------------------- -- subtracter 1 output signal sub1_out : std_logic_vector( 7 downto 0); -- multiplier 1 output signal mult1_out : std_logic_vector( 8 downto 0); -- multiplier 2 output signal mult2_out : std_logic_vector( 3 downto 0); -- adder 1 output signal add1_out : std_logic_vector( 7 downto 0); -- address used with image signal pos_img : std_logic_vector( 8 downto 0); -- address used with mask signal pos_mask : std_logic_vector( 3 downto 0); -- image output data signal img_point : std_logic_vector( 8 downto 0); -- mask output data signal mask_point : std_logic_vector( 5 downto 0); -- multiplier 3 output signal mult3_out : std_logic_vector(15 downto 0); -- adder 4 output signal add4_out : std_logic_vector(16 downto 0); -- accumulator of 1 pt signal onePTcontrib : std_logic_vector(15 downto 0); -- output of subtracter used on 'max' calculus signal out_sub_max : std_logic_vector(16 downto 0); -- output of subtracter used on 'min' calculus signal out_sub_min : std_logic_vector(16 downto 0); -- ------------------------------------------------------------------- -- /OE (LOAD) signals used to read (write) from (to) the FPGA -- through the PCI bus -- ------------------------------------------------------------------- signal not_oe_line_outL : std_logic; signal not_oe_line_outM : std_logic; signal not_oe_maxL : std_logic; signal not_oe_maxM : std_logic; signal not_oe_minL : std_logic; signal not_oe_minM : std_logic; signal not_oe_accept3l : std_logic; signal not_oe_conv1line_done : std_logic; signal not_oe_convol_done : std_logic; signal load_lines_in : STD_LOGIC; signal load_read_done : STD_LOGIC; signal load_write_done : STD_LOGIC; signal load_written3l : STD_LOGIC; signal load_wr_finished : STD_LOGIC; signal load_start_fsm : STD_LOGIC; signal load_reset_ff : STD_LOGIC; -- ------------------------------------------------------------------- begin ----------------------------------------------------------------- clk <= PCLOCK_I ; not_oe_d <= not_oe_line_outL and not_oe_line_outM and not_oe_maxL and not_oe_maxM and not_oe_minL and not_oe_minM and not_oe_accept3l and not_oe_conv1line_done and not_oe_convol_done ; not_oe_d2c <= '1' ; -- (if DATA2CPLD[] pins are used CHANGE this) not_oe_dup <= '1' ; -- (if DATA_UP[] pins are used CHANGE this) not_oe_ddwn <= '1' ; -- (if DATA_DWN[] pins are used CHANGE this) not_oe_gen <= '1' ; -- (if GENERICO[] pins are used CHANGE this) not_oe_conn <= '1' ; -- (if CONNECTOR[] pins are used CHANGE this) ----------------------------------------------------------------- -- Fixed Parameters -- ----------------------------------------------------------------- sig_gnd <= '0'; sig_vcc <= '1'; tx <= "100000000"; -- tx = 256 pixeis ty <= "100000000"; -- ty = 256 pixeis maskX <= "11"; -- maskX = 3 pixeis maskY <= "11"; -- maskY = 3 pixeis mcolumn(6 downto 2) <= "00000"; img_point(8) <= '0'; mult3_out(15) <= mult3_out(14); ----------------------------------------------------------------- -- COMPUTE a, colunas, start_line, start_column, start_mline, -- -- start_mcolumn -- ----------------------------------------------------------------- process(tx, ty, maskX, maskY) variable a_tmp : std_logic_vector(6 downto 0); variable colunas_tmp : std_logic_vector(8 downto 0); begin -- a_tmp(1 downto 0) := maskX/2; -- a_tmp(6 downto 2) := "00000"; -- colunas_tmp := tx/4 + 2; -- start_line <= ty-2; -- start_column <= colunas_tmp-1-a_tmp; -- start_mline <= maskY; -- start_mcolumn(1 downto 0) <= maskX; -- start_mcolumn(6 downto 2) <= "00000"; a_tmp(1 downto 0) := int_2_std_logic_vector ( (std_logic_vector_2_posint(maskX)/2),2); a_tmp(6 downto 2) := "00000"; colunas_tmp := int_2_std_logic_vector ( ((std_logic_vector_2_posint(tx)/4)+2),9); start_line <= int_2_std_logic_vector ( (std_logic_vector_2_posint(ty)-2),9); start_column <= int_2_std_logic_vector ( (std_logic_vector_2_posint(colunas_tmp)-1- std_logic_vector_2_posint(a_tmp)),7); start_mline <= maskY; start_mcolumn(1 downto 0) <= maskX; start_mcolumn(6 downto 2) <= "00000"; a <= a_tmp; colunas <= colunas_tmp(6 downto 0); end process; ------------------- -- reset_ff F/F -- ------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_I(0) -- Qout: reset_ff -- CLOCK: clk -- CE: load_reset_ff RST_FF: ffd_ce port map ( data_in => DATA_I(0) , clock => clk , enable => load_reset_ff , data_out => reset_ff ); ------------------- -- start_fsm F/F -- ------------------- -- -- RESET: reset_ff -- SET: --- -- Din: DATA_I(0) -- Qout: start_fsm -- CLOCK: clk -- CE: load_start_fsm SFSM_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => load_start_fsm , reset => reset_ff , data_out => start_fsm ); ------------------- -- read_done F/F -- ------------------- -- -- RESET: reset_ff -- SET: --- -- Din: DATA_I(0) -- Qout: read_done -- CLOCK: clk -- CE: load_read_done RDONE_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => load_read_done , reset => reset_ff , data_out => read_done ); -------------------- -- write_done F/F -- -------------------- -- -- RESET: reset_ff -- SET: --- -- Din: DATA_I(0) -- Qout: write_done -- CLOCK: clk -- CE: load_write_done WDONE_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => load_write_done , reset => reset_ff , data_out => write_done ); --------------------- -- wr_finished F/F -- --------------------- -- -- RESET: reset_ff -- SET: --- -- Din: DATA_I(0) -- Qout: wr_finished -- CLOCK: clk -- CE: load_wr_finished WFINISH_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => load_wr_finished , reset => reset_ff , data_out => wr_finished ); ------------------- -- written3l F/F -- ------------------- -- -- RESET: reset_ff -- SET: --- -- Din: DATA_I(0) -- Qout: written3l -- CLOCK: clk -- CE: load_written3l WR3L_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => load_written3l , reset => reset_ff , data_out => written3l ); --------------------- -- convol_done F/F -- --------------------- -- -- RESET: rst_cdone_ored=1 -- SET: set_cdone=1 -- Din: convol_done -- Qout: convol_done -- CLOCK: clk -- CE: --- rst_cdone_ored <= rst_cdone_max_min or reset_ff; CONVD_FF: ffd_rst_syncset port map ( data_in => convol_done , clock => clk , reset => rst_cdone_ored , set => set_cdone , data_out => convol_done ); -- connect F/F to the PCI data bus process(not_oe_convol_done, convol_done) begin if (not_oe_convol_done = '0') then DATA_O(0) <= convol_done ; else DATA_O(0) <= 'Z' ; end if ; end process; -- --------------------- -- conv1line_done F/F -- ------------------------ -- -- RESET: rst_cdonel_ored=1 -- SET: set_cdonel=1 -- Din: conv1line_done -- Qout: conv1line_done -- CLOCK: clk -- CE: --- rst_cdonel_ored <= rst_cdonel or reset_ff; CONV1LD_FF: ffd_rst_syncset port map ( data_in => conv1line_done , clock => clk , reset => rst_cdonel_ored , set => set_cdonel , data_out => conv1line_done ); -- connect F/F to the PCI data bus process(not_oe_conv1line_done, conv1line_done) begin if (not_oe_conv1line_done = '0') then DATA_O(0) <= conv1line_done ; else DATA_O(0) <= 'Z' ; end if ; end process; ------------------ -- accept3l F/F -- ------------------ -- -- RESET: rst_a3l_ored=1 -- SET: set_a3l=1 -- Din: accept3l -- Qout: accept3l -- CLOCK: clk -- CE: --- rst_a3l_ored <= rst_a3l or reset_ff; ACCEPT3L_FF: ffd_rst_syncset port map ( data_in => accept3l , clock => clk , reset => rst_a3l_ored , set => set_a3l , data_out => accept3l ); -- connect F/F to the PCI data bus process(not_oe_accept3l, accept3l) begin if (not_oe_accept3l = '0') then DATA_O(0) <= accept3l ; else DATA_O(0) <= 'Z' ; end if ; end process; ---------------------------------- -- onePTcontrib 16-BIT REGISTER -- ---------------------------------- -- -- RESET: rst_1ptcontrib=1 (from CPLD) -- SET: --- -- Din: add4_out(15 downto 0) -- Qout: onePTcontrib -- CLOCK: clk -- CE: ce_1ptcontrib process (clk, rst_1ptcontrib) begin if (rst_1ptcontrib = '1') then onePTcontrib <= "0000000000000000"; elsif (clk'event and clk = '1') then if (ce_1ptcontrib = '1') then onePTcontrib <= add4_out(15 downto 0); end if; end if; end process; ------------------------------------------------------------ -- mascara ROM [0:15] 6-BIT -- -- -- ROM 16 x 6-bit generated with LOGIBLOX (rom16x6.ngc file) ------------------------------------------------------------ -- -- Qout: mask_point ( 5 downto 0 ) -- ADDRESS: pos_mask ( 3 downto 0 ) -- MASK : rom16x6 port map ( A => pos_mask , DO => mask_point ); ------------------------------------ -- lines_in RAM [0:207] 8-BIT -- ------------------------------------ -- -- Din: DATA_I (7 downto 0) -- Qout: img_point (7 downto 0) -- CLOCK: clk -- WE: load_lines_in -- WRITE ADDRESS: ADDR_I (9 downto 2) -- READ ADDRESS: pos_img (7 downto 0) LINES_IN: ram_208x8 port map ( d => DATA_I , add_rd => pos_img(7 downto 0) , add_wr => ADDR_I(9 downto 2) , clk => clk , we => load_lines_in , sel_add => written3l , o => img_point(7 downto 0) ); ------------------------------------ -- line_out RAM [0:79] 16-BIT -- ------------------------------------ -- -- OPERATION: line_out(column) <= onePTcontrib -- Din: onePTcontrib (15 downto 0) -- Qout: DATA_O ( 7 downto 0) -- CLOCK: clk -- WE: we_store1pt -- WRITE ADDRESS: column ( 6 downto 0) -- READ ADDRESS: ADDR_I(8 downto 2) to RAM, ADDR(9) to generate /OE's LINE_OUT: ram_80x16 port map ( d => onePTcontrib , add_rd => ADDR_I(8 downto 2) , add_wr => column , clk => clk , we => we_store1pt , written3l => written3l , conv1line_done => conv1line_done , not_oe_lsb => not_oe_line_outL , not_oe_msb => not_oe_line_outM , o => DATA_O ); --------------------------------------------------------- -- 8-BIT DOWN COUNTER USED TO STORE LINE NUMBER (line) -- -- START VALUE: start_line (= ty-2 ) -- CLOCK: clk_line (from CPLD) -- LOAD: load_line (from CPLD) -- RESET: reset_ff -- COUNT: line -- COUNTING: counting_l -------------------------------------------------------- COUNTER_L: counterDown generic map (w => 8) port map ( start => start_line(7 downto 0) , c => clk_line , load => load_line , reset => reset_ff , count => line(7 downto 0) , counting => counting_l ); ------------------------------------------------------------- -- 7-BIT DOWN COUNTER USED TO STORE COLUMN NUMBER (column) -- -- START VALUE: start_column (= colunas-1-a ) -- STOP VALUE: 0 (= a-1 = 0 ) -- CLOCK: clk_column (from CPLD ) -- LOAD: load_column (from CPLD ) -- RESET: reset_ff -- COUNT: column -- COUNTING: counting_c ------------------------------------------------------------ COUNTER_C: counterDown generic map (w => 7) port map ( start => start_column(6 downto 0) , c => clk_column , load => load_column , reset => reset_ff , count => column(6 downto 0) , counting => counting_c ); --------------------------------------------------------------- -- 2-BIT DOWN COUNTER USED TO STORE MASK LINE NUMBER (mline) -- -- START VALUE: start_mline (= maskY ) -- CLOCK: clk_mline (from CPLD) -- LOAD: load_mline (from CPLD) -- RESET: reset_ff -- COUNT: mline -- COUNTING: counting_ml --------------------------------------------------------------- COUNTER_ML: counterDown generic map (w => 2) port map ( start => start_mline(1 downto 0) , c => clk_mline , load => load_mline , reset => reset_ff , count => mline(1 downto 0) , counting => counting_ml ); ------------------------------------------------------------------- -- 2-BIT DOWN COUNTER USED TO STORE MASK COLUMN NUMBER (mcolumn) -- -- START VALUE: start_mcolumn (=maskX ) -- CLOCK: clk_mcolumn (from CPLD) -- LOAD: load_mcolumn (from CPLD) -- RESET: reset_ff -- COUNT: mcolumn -- COUNTING: counting_mc ------------------------------------------------------------------- COUNTER_MC: counterDown generic map (w => 2) port map ( start => start_mcolumn(1 downto 0) , c => clk_mcolumn , load => load_mcolumn , reset => reset_ff , count => mcolumn(1 downto 0) , counting => counting_mc ); -- -------------------------------------- -- max 16-BIT REGISTER -- -------------------------------------- -- -- LOAD WITH "0..01": rst_cdone_max_min=1 (from CPLD) -- SET/RESET: rst_cdone_max_min -- Din: onePTcontrib -- Qout: max -- CLOCK: clk -- CE: ce_max SUB_MAX: signed_r_sub generic map (w => 16) port map ( a => onePTcontrib , b => max , clk => clk , ce => sig_vcc , bi => sig_gnd , reset => reset_ff , r => out_sub_max ); update_max <= not(out_sub_max(16)); ce_max <= update_max and we_store1pt; process (clk, rst_cdone_max_min) begin if (rst_cdone_max_min = '1') then max <= "0000000000000001"; elsif (clk'event and clk = '1') then if (ce_max = '1') then max <= onePTcontrib; end if; end if; end process; process(not_oe_maxL, max) begin if (not_oe_maxL = '0') then DATA_O <= max(7 downto 0) ; else DATA_O <= "ZZZZZZZZ" ; end if ; end process; process(not_oe_maxM, max) begin if (not_oe_maxM = '0') then DATA_O <= max(15 downto 8) ; else DATA_O <= "ZZZZZZZZ" ; end if ; end process; -- -------------------------------------- -- min 16-BIT REGISTER -- -------------------------------------- -- -- RESET: rst_cdone_max_min=1 (from CPLD) -- SET: --- -- Din: onePTcontrib -- Qout: min -- CLOCK: clk -- CE: ce_min SUB_MIN: signed_r_sub generic map (w => 16) port map ( a => onePTcontrib , b => min , clk => clk , ce => sig_vcc , bi => sig_gnd , reset => reset_ff , r => out_sub_min ); update_min <= out_sub_min(16); ce_min <= update_min and we_store1pt; process (clk, rst_cdone_max_min) begin if (rst_cdone_max_min = '1') then min <= "0000000000000000"; elsif (clk'event and clk = '1') then if (ce_min = '1') then min <= onePTcontrib; end if; end if; end process; process(not_oe_minL, min) begin if (not_oe_minL = '0') then DATA_O <= min(7 downto 0) ; else DATA_O <= "ZZZZZZZZ" ; end if ; end process; process(not_oe_minM, min) begin if (not_oe_minM = '0') then DATA_O <= min(15 downto 8) ; else DATA_O <= "ZZZZZZZZ" ; end if ; end process; -- -------------------------------------- -- 7-bit unsigned subtracter -- -------------------------------------- SUB1: unsigned_r_sub generic map (w => 7) port map ( a => column , b => a , c => clk , ce => ce_s1_m1_m2 , bi => sig_gnd , clr => reset_ff , r => sub1_out ); -- -------------------------------------- -- 7-bit unsigned adder -- -------------------------------------- ADD1: unsigned_r_add generic map (w => 7) port map ( a => sub1_out(6 downto 0) , b => mcolumn , c => clk , ce => ce_a1_a2 , ci => sig_gnd , clr => reset_ff , s => add1_out ); -- -------------------------------------- -- 3-bit unsigned adder ----------------------------------------- -- pos_mask 4-BIT REGISTER ----------------------------------------- ADD2: unsigned_r_add generic map (w => 3) port map ( a => mcolumn(2 downto 0) , b => mult2_out(2 downto 0) , c => clk , ce => ce_a1_a2 , ci => sig_gnd , clr => reset_ff , s => pos_mask ); -- -------------------------------------- -- 8-bit unsigned adder ----------------------------------------- -- pos_img 9-BIT REGISTER (8-bit usefull) ----------------------------------------- ADD3: unsigned_r_add generic map (w => 8) port map ( a => add1_out , b => mult1_out(7 downto 0) , c => clk , ce => ce_add3 , ci => sig_gnd , clr => reset_ff , s => pos_img ); -- -------------------------------------- -- 16-bit signed adder -- -------------------------------------- ADD4: sign_r_add generic map (w => 16) port map ( a => onePTcontrib , b => mult3_out , c => clk , ce => ce_add4 , ci => sig_gnd , clr => reset_ff , s => add4_out ); -- -------------------------------------- -- 7-bit x 2-bit unsigned multiplier -- -------------------------------------- MULT1: unsigned_mult generic map ( aw => 7 , bw => 2 ) port map ( a => colunas , b => mline , c => clk , ce => ce_s1_m1_m2 , reset => reset_ff , prod => mult1_out ); -- -------------------------------------- -- 2-bit x 2-bit unsigned multiplier -- -------------------------------------- MULT2: unsigned_mult generic map ( aw => 2 , bw => 2 ) port map ( a => mline , b => maskX , c => clk , ce => ce_s1_m1_m2 , reset => reset_ff , prod => mult2_out ); -- -------------------------------------- -- 9-bit x 6-bit signed multiplier -- -------------------------------------- MULT3: signed_mult generic map ( aw => 9 , bw => 6 ) port map ( a => img_point , b => mask_point , c => clk , ce => ce_mult3 , reset => reset_ff , prod => mult3_out(14 downto 0) ); -- ------------------------------------------------------------------- -- Generation of the /OE (LOAD) signals used to read (write) from -- (to) the FPGA through the PCI bus -- ------------------------------------------------------------------- CTL_INTERF: ctl_fpga_interface port map ( NOTWR_I => NOTWR_I , NOTRD_I => NOTRD_I , RESET_I => RESET_I , PCLOCK_I => PCLOCK_I , BASE_HIT0_I => BASE_HIT0_I , ADDR_VLD_I => ADDR_VLD_I , S_DATA_VLD_I => S_DATA_VLD_I , PCI_CMD7_I => PCI_CMD7_I , PCI_CMD6_I => PCI_CMD6_I , ADDR_I => ADDR_I , S_DATA_I => S_DATA_I , not_oe_line_outL => not_oe_line_outL , not_oe_line_outM => not_oe_line_outM , not_oe_maxL => not_oe_maxL , not_oe_maxM => not_oe_maxM , not_oe_minL => not_oe_minL , not_oe_minM => not_oe_minM , not_oe_accept3l => not_oe_accept3l , not_oe_conv1line_done => not_oe_conv1line_done , not_oe_convol_done => not_oe_convol_done , load_lines_in => load_lines_in , load_read_done => load_read_done , load_write_done => load_write_done , load_written3l => load_written3l , load_wr_finished => load_wr_finished , load_start_fsm => load_start_fsm , load_reset_ff => load_reset_ff ); -- ------------------------------------------------------------------- -- FSM THAT CONTROLS THE EXECUTION OF THE CONVOLUTION PART -- ALLOCATED TO EACH FPGA -- ------------------------------------------------------------------- FSM_CONVOL: fsm port map ( clk => clk , reset_ff => reset_ff , start_fsm => start_fsm , read_done => read_done , write_done => write_done , written3l => written3l , wr_finished => wr_finished , counting_l => counting_l , counting_c => counting_c , counting_ml => counting_ml , counting_mc => counting_mc , rst_a3l => rst_a3l , rst_cdone_max_min => rst_cdone_max_min , rst_cdonel => rst_cdonel , rst_1ptcontrib => rst_1ptcontrib , set_cdone => set_cdone , set_a3l => set_a3l , set_cdonel => set_cdonel , load_line => load_line , load_column => load_column , load_mline => load_mline , load_mcolumn => load_mcolumn , clk_line => clk_line , clk_column => clk_column , clk_mline => clk_mline , clk_mcolumn => clk_mcolumn , we_store1pt => we_store1pt , ce_s1_m1_m2 => ce_s1_m1_m2 , ce_a1_a2 => ce_a1_a2 , ce_add3 => ce_add3 , ce_mult3 => ce_mult3 , ce_add4 => ce_add4 , ce_1ptcontrib => ce_1ptcontrib ); -- -------------------------------------------------------------- -- interface with the module that instantiates the FPGA PADs -- -------------------------------------------------------------- INTERF: fpga_interface port map ( -- signals connecting the fpga to the exterior NOTWR => NOTWR , NOTRD => NOTRD , RESET => RESET , PCLOCK => PCLOCK , SCLOCK => SCLOCK , BASE_HIT0 => BASE_HIT0 , ADDR_VLD => ADDR_VLD , S_DATA_VLD => S_DATA_VLD , PCI_CMD7 => PCI_CMD7 , PCI_CMD6 => PCI_CMD6 , S_CBE => S_CBE , ADDR => ADDR , DATA => DATA , S_SRC_EN => S_SRC_EN , S_DATA => S_DATA , DATA_UP => DATA_UP , -- (32 downto 0) DATA_DWN => DATA_DWN , -- (32 downto 0) CONNECTOR => CONNECTOR , -- (15 downto 0) DATA2CPLD => DATA2CPLD , -- ( 7 downto 0) CLK_CPLD => CLK_CPLD , -- ( 1 downto 0) CLK_DWN_OUT => CLK_DWN_OUT , CLK_DWN_IN => CLK_DWN_IN , CLK_UP_OUT => CLK_UP_OUT , CLK_UP_IN => CLK_UP_IN , GENERICO => GENERICO , -- ( 2 downto 1) -- signals connecting to the rest of the fpga logic NOTWR_I => NOTWR_I , NOTRD_I => NOTRD_I , RESET_I => RESET_I , PCLOCK_I => PCLOCK_I , SCLOCK_I => SCLOCK_I , BASE_HIT0_I => BASE_HIT0_I , ADDR_VLD_I => ADDR_VLD_I , S_DATA_VLD_I => S_DATA_VLD_I , PCI_CMD7_I => PCI_CMD7_I , PCI_CMD6_I => PCI_CMD6_I , S_CBE_I => S_CBE_I , ADDR_I => ADDR_I , -- (17 downto 0) DATA_I => DATA_I , -- ( 7 downto 0) DATA_O => DATA_O , -- ( 7 downto 0) S_SRC_EN_I => S_SRC_EN_I , S_DATA_I => S_DATA_I , DATA_UP_O => DATA_UP_O , -- (32 downto 0) DATA_UP_I => DATA_UP_I , -- (32 downto 0) CONNECTOR_O => CONNECTOR_O , -- (15 downto 0) CONNECTOR_I => CONNECTOR_I , -- (15 downto 0) DATA_DWN_O => DATA_DWN_O , -- (32 downto 0) DATA_DWN_I => DATA_DWN_I , -- (32 downto 0) DATA2CPLD_O => DATA2CPLD_O , -- ( 7 downto 0) DATA2CPLD_I => DATA2CPLD_I , -- ( 7 downto 0) CLK_CPLD_I => CLK_CPLD_I , -- ( 1 downto 0) CLK_DWN_OUT_O => CLK_DWN_OUT_O , CLK_DWN_IN_I => CLK_DWN_IN_I , CLK_UP_OUT_O => CLK_UP_OUT_O , CLK_UP_IN_I => CLK_UP_IN_I , GENERICO_O => GENERICO_O , -- ( 2 downto 1) GENERICO_I => GENERICO_I , -- ( 2 downto 1) -- signals to control tri-state buffers of bi-direccional pins not_oe_d => not_oe_d , not_oe_d2c => not_oe_d2c , not_oe_dup => not_oe_dup , not_oe_ddwn => not_oe_ddwn , not_oe_gen => not_oe_gen , not_oe_conn => not_oe_conn ); end structural ; -- =======================================================================