-- =======================================================================
-- Author:  Antonio Esteves, GEC-DI-UM.
-- File:    lib_hw.vhd
-- Date:    09 August 2000
-- =======================================================================

LIBRARY ieee;
USE     ieee.std_logic_1164.ALL;

PACKAGE functions_util IS

-- -------------------------------------------------------------------- --
-- FUNCTION PROTOTYPES                                                  --
-- -------------------------------------------------------------------- --

  FUNCTION std_logic_vector_2_posint(vect : std_logic_vector )
    RETURN INTEGER;

  FUNCTION int_2_std_logic_vector( value, bitwidth : INTEGER )
    RETURN std_logic_vector;

  FUNCTION two_comp(vect : std_logic_vector )
    RETURN std_logic_vector;

  FUNCTION sign_extend( vector : std_logic_vector; bits : INTEGER )
    RETURN std_logic_vector;
  
end functions_util;

PACKAGE BODY functions_util IS

-- -------------------------------------------------------------------- --
-- FUNCTIONS                                                            --
-- -------------------------------------------------------------------- --

-- -------------------------------------------------------------------- --

  FUNCTION std_logic_vector_2_posint(vect : std_logic_vector)
    RETURN INTEGER IS

    variable result : INTEGER;

  BEGIN
    result := 0;
    FOR i in vect'HIGH downto vect'LOW LOOP
      result := result * 2;
      IF (vect(i) = '1') THEN
        result := result + 1;
      END IF;
    END LOOP;
    RETURN result;
  END std_logic_vector_2_posint;

-- -------------------------------------------------------------------- --

  FUNCTION int_2_std_logic_vector( value, bitwidth : INTEGER )
    RETURN std_logic_vector IS

    VARIABLE running_value  : INTEGER;
    VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);

  BEGIN
    running_value  := value;
    IF (value < 0) THEN
      running_value := -1 * value;
    END IF;
    FOR i IN 0 TO bitwidth-1 LOOP
      IF running_value MOD 2 = 0 THEN
        running_result(i) := '0';
      ELSE
        running_result(i) := '1';
      END IF;
      running_value := running_value/2;
    END LOOP;
    IF (value < 0) THEN -- find the 2s complement
       RETURN two_comp(running_result);
    ELSE
      RETURN running_result;
    END IF;
  END int_2_std_logic_vector;

-- -------------------------------------------------------------------- --

  FUNCTION two_comp(vect : std_logic_vector)
    RETURN std_logic_vector IS

  variable local_vect : std_logic_vector(vect'HIGH downto 0);
  variable toggle : INTEGER;

  BEGIN
    toggle := 0;
    FOR i IN 0 to vect'HIGH LOOP
      IF (toggle = 1) THEN
        IF (vect(i) = '0') THEN
          local_vect(i) := '1';
        ELSE
          local_vect(i) := '0';
        END IF;
      ELSE
        local_vect(i) := vect(i);
         IF (vect(i) = '1') THEN
           toggle := 1;
         END IF;
      END IF;
    END LOOP;
    RETURN local_vect;
  END two_comp;

  -- ---------------------------------------------------------------- --
  -- Sign-extended a bit vector to the designated width
  -- ---------------------------------------------------------------- --

  FUNCTION sign_extend( vector : std_logic_vector; bits : integer )
    RETURN std_logic_vector IS

  VARIABLE return_value :  
    std_logic_vector (bits-1+vector'low DOWNTO vector'low);

  BEGIN

    return_value(vector'high downto return_value'low) := vector;
  
    FOR i IN vector'high+1 TO return_value'high LOOP
      return_value(i) := vector(vector'high);
    END LOOP;

    RETURN return_value;

  END sign_extend;
  
-- -------------------------------------------------------------------- --

END functions_util;