-- ======================================================================= -- Author: Antonio Esteves, GEC-DI-UM. -- File: interface_ctl.vhd -- Date: 13 August 2000 -- -- Component allocated to an FPGA for the hw/sw convolution implementation. -- Synthesizable version. -- -- MODULE THAT GENERATES THE CONTROL SIGNALS USED TO READ (WRITE) FROM -- (TO) THE FPGA THROUGH THE PCI BUS. -- ======================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; -- +-------------------------+---------+-----+----+--------+--------+ -- | SIGNAL | A17 A16 | A15 | A9 | A8..A5 | A4A3A2 | -- +-------------------------+---------+-----+----+--------+--------+ -- | not_oe_line_outL | 0 0 | 1 | 0 | xxxx | xxx | -- | not_oe_line_outM | 0 0 | 1 | 1 | xxxx | xxx | -- | not_oe_maxL | 0 1 | - | - | ---- | 000 | -- | not_oe_maxM | 0 1 | - | - | ---- | 001 | -- | not_oe_minL | 0 1 | - | - | ---- | 010 | -- | not_oe_minM | 0 1 | - | - | ---- | 011 | -- | not_oe_accept3l | 0 1 | - | - | ---- | 100 | -- | not_oe_conv1line_done | 0 1 | - | - | ---- | 101 | -- | not_oe_convol_done | 0 1 | - | - | ---- | 110 | -- +-------------------------+---------+-----+----+--------+--------+ -- | load_lines_in | 0 0 | 0 | x | xxxx | xxx | -- | load_read_done | 0 1 | - | - | ---- | 000 | -- | load_write_done | 0 1 | - | - | ---- | 001 | -- | load_wr_finished | 0 1 | - | - | ---- | 010 | -- | load_written3l | 0 1 | - | - | ---- | 011 | -- | load_reset_ff | 0 1 | - | - | ---- | 100 | -- | load_start_fsm | 0 1 | - | - | ---- | 101 | -- +-------------------------+---------+-----+----+--------+--------+ -- ------------------------------------------------------------------ -- FPGA INTERFACE CONTROLLER entity entity ctl_fpga_interface is port ( NOTWR_I : in std_logic ; NOTRD_I : in std_logic ; RESET_I : in std_logic ; PCLOCK_I : in std_logic ; BASE_HIT0_I : in std_logic ; ADDR_VLD_I : in std_logic ; S_DATA_VLD_I : in std_logic ; PCI_CMD7_I : in std_logic ; PCI_CMD6_I : in std_logic ; ADDR_I : in std_logic_vector(17 downto 0) ; S_DATA_I : in std_logic ; not_oe_line_outL : out std_logic; not_oe_line_outM : out std_logic; not_oe_maxL : out std_logic; not_oe_minL : out std_logic; not_oe_maxM : out std_logic; not_oe_minM : out std_logic; not_oe_accept3l : out std_logic; not_oe_conv1line_done : out std_logic; not_oe_convol_done : out std_logic; load_lines_in : out STD_LOGIC; load_read_done : out STD_LOGIC; load_write_done : out STD_LOGIC; load_written3l : out STD_LOGIC; load_wr_finished : out STD_LOGIC; load_start_fsm : out STD_LOGIC; load_reset_ff : out STD_LOGIC ); end ctl_fpga_interface ; -- end of FPGA INTERFACE CONTROLLER entity -- -------------------------------------------------------------- architecture ffs_e_muxes of ctl_fpga_interface is signal delayed_reset, global_deassert, q_deassert : std_logic ; -- LSByte of ram LINE_OUT signal cs_rd_line_outL, rst_rd_line_outL, set_rd_line_outL, d_rd_line_outL, not_oe_rd_line_outL : std_logic ; -- MSByte of ram LINE_OUT signal cs_rd_line_outM, rst_rd_line_outM, set_rd_line_outM, d_rd_line_outM, not_oe_rd_line_outM : std_logic ; -- LSByte of register MAX signal cs_rd_maxL, rst_rd_maxL, set_rd_maxL, d_rd_maxL, not_oe_rd_maxL : std_logic ; -- MSByte of register MAX signal cs_rd_maxM, rst_rd_maxM, set_rd_maxM, d_rd_maxM, not_oe_rd_maxM : std_logic ; -- LSByte of register MIN signal cs_rd_minL, rst_rd_minL, set_rd_minL, d_rd_minL, not_oe_rd_minL : std_logic ; -- MSByte of register MIN signal cs_rd_minM, rst_rd_minM, set_rd_minM, d_rd_minM, not_oe_rd_minM : std_logic ; -- flip-flop ACCEPT3L signal cs_rd_accept3l, rst_rd_accept3l, set_rd_accept3l, d_rd_accept3l, not_oe_rd_accept3l : std_logic ; -- flip-flop CONV1LINE_DONE signal cs_rd_conv1line_done, rst_rd_conv1line_done, set_rd_conv1line_done, d_rd_conv1line_done, not_oe_rd_conv1line_done : std_logic ; -- flip-flop CONVOL_DONE signal cs_rd_convol_done, rst_rd_convol_done, set_rd_convol_done, d_rd_convol_done, not_oe_rd_convol_done : std_logic ; -- ram ram LINES_IN signal cs_wr_lines_in, set_wr_lines_in, rst_wr_lines_in, load_wr_lines_in, d1_wr_lines_in, q1_wr_lines_in : std_logic ; -- flip-flop READ_DONE signal cs_wr_read_done, set_wr_read_done, rst_wr_read_done, load_wr_read_done, d1_wr_read_done, q1_wr_read_done : std_logic; -- flip-flop WRITE_DONE signal cs_wr_write_done, set_wr_write_done, rst_wr_write_done, load_wr_write_done, d1_wr_write_done, q1_wr_write_done: std_logic; -- flip-flop WR_FINISHED signal cs_wr_wr_finished, set_wr_wr_finished, rst_wr_wr_finished, load_wr_wr_finished, d1_wr_wr_finished, q1_wr_wr_finished : std_logic ; -- flip-flop WRITTEN3L signal cs_wr_written3l, set_wr_written3l, rst_wr_written3l, load_wr_written3l, d1_wr_written3l, q1_wr_written3l : std_logic ; -- flip-flop RESET_FF signal cs_wr_reset_ff, set_wr_reset_ff, rst_wr_reset_ff, load_wr_reset_ff, d1_wr_reset_ff, q1_wr_reset_ff : std_logic ; -- flip-flop START_FSM signal cs_wr_start_fsm, set_wr_start_fsm, rst_wr_start_fsm, load_wr_start_fsm, d1_wr_start_fsm, q1_wr_start_fsm : std_logic ; begin not_oe_line_outL <= not_oe_rd_line_outL; not_oe_line_outM <= not_oe_rd_line_outM; not_oe_maxL <= not_oe_rd_maxL; not_oe_maxM <= not_oe_rd_maxM; not_oe_minL <= not_oe_rd_minL; not_oe_minM <= not_oe_rd_minM; not_oe_accept3l <= not_oe_rd_accept3l; not_oe_conv1line_done <= not_oe_rd_conv1line_done; not_oe_convol_done <= not_oe_rd_convol_done; load_lines_in <= load_wr_lines_in; load_read_done <= load_wr_read_done; load_write_done <= load_wr_write_done; load_written3l <= load_wr_written3l; load_wr_finished <= load_wr_wr_finished; load_start_fsm <= load_wr_start_fsm; load_reset_ff <= load_wr_reset_ff; -- ------------------------------------------------------------- delayed_reset <= RESET_I ; -- ------------------------------------------------------------- -- Generation of a global signal that will be used to -- -- deassert (put high) all the output enable's (active low) -- -- ------------------------------------------------------------- -- flip-flop process (S_DATA_I, ADDR_VLD_I, delayed_reset) begin if ( (ADDR_VLD_I='1') or (delayed_reset='1') ) then -- reset q_deassert <= '0' ; elsif (S_DATA_I'event and S_DATA_I='0') then -- falling edge clock q_deassert <= '1' ; end if; end process; global_deassert <= delayed_reset or q_deassert or (ADDR_VLD_I and (not PCLOCK_I)) ; -- ----------------------------------------------------------------- -- "output enable" to read LSbyte of LINE_OUT ram (/OE) -- -- ADDR[17:0] = 00 1xxx xx0x xxxx xxxx = (08000 hex + RAM offset) -- -- ----------------------------------------------------------------- cs_rd_line_outL <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(15) and (not ADDR_I(9)); rst_rd_line_outL <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_line_outL and (not PCLOCK_I) ) ; set_rd_line_outL <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_line_outL, not_oe_rd_line_outL) begin if (set_rd_line_outL='0') then d_rd_line_outL <= not_oe_rd_line_outL ; else d_rd_line_outL <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_line_outL, PCLOCK_I) begin if (rst_rd_line_outL='1') then not_oe_rd_line_outL <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_line_outL <= d_rd_line_outL ; end if; end process; -- ----------------------------------------------------------------- -- "output enable" to read MSbyte of LINE_OUT ram (/OE) -- -- ADDR[17:0] = 00 1xxx xx1x xxxx xxxx = (08200 hex + RAM offset) -- -- ----------------------------------------------------------------- cs_rd_line_outM <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(15) and ADDR_I(9); rst_rd_line_outM <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_line_outM and (not PCLOCK_I) ) ; set_rd_line_outM <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_line_outM, not_oe_rd_line_outM) begin if (set_rd_line_outM='0') then d_rd_line_outM <= not_oe_rd_line_outM ; else d_rd_line_outM <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_line_outM, PCLOCK_I) begin if (rst_rd_line_outM='1') then not_oe_rd_line_outM <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_line_outM <= d_rd_line_outM ; end if; end process; -- ------------------------------------------------------- -- "output enable" to read LSbyte of MAX register (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 00xx = 10000 hex -- -- ------------------------------------------------------- cs_rd_maxL <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and (not ADDR_I(3)) and (not ADDR_I(2)) ; rst_rd_maxL <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_maxL and (not PCLOCK_I) ) ; set_rd_maxL <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_maxL, not_oe_rd_maxL) begin if (set_rd_maxL='0') then d_rd_maxL <= not_oe_rd_maxL ; else d_rd_maxL <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_maxL, PCLOCK_I) begin if (rst_rd_maxL='1') then not_oe_rd_maxL <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_maxL <= d_rd_maxL ; end if; end process; -- ------------------------------------------------------- -- "output enable" to read MSbyte of MAX register (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 01xx = 10004 hex -- -- ------------------------------------------------------- cs_rd_maxM <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and (not ADDR_I(3)) and ADDR_I(2) ; rst_rd_maxM <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_maxM and (not PCLOCK_I) ) ; set_rd_maxM <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_maxM, not_oe_rd_maxM) begin if (set_rd_maxM='0') then d_rd_maxM <= not_oe_rd_maxM ; else d_rd_maxM <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_maxM, PCLOCK_I) begin if (rst_rd_maxM='1') then not_oe_rd_maxM <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_maxM <= d_rd_maxM ; end if; end process; -- ------------------------------------------------------- -- "output enable" to read LSbyte of MIN register (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 10xx = 10008 hex -- -- ------------------------------------------------------- cs_rd_minL <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and ADDR_I(3) and (not ADDR_I(2)) ; rst_rd_minL <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_minL and (not PCLOCK_I) ) ; set_rd_minL <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_minL, not_oe_rd_minL) begin if (set_rd_minL='0') then d_rd_minL <= not_oe_rd_minL ; else d_rd_minL <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_minL, PCLOCK_I) begin if (rst_rd_minL='1') then not_oe_rd_minL <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_minL <= d_rd_minL ; end if; end process; -- ------------------------------------------------------- -- "output enable" to read MSbyte of MIN register (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 11xx = 1000C hex -- -- ------------------------------------------------------- cs_rd_minM <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and ADDR_I(3) and ADDR_I(2) ; rst_rd_minM <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_minM and (not PCLOCK_I) ) ; set_rd_minM <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_minM, not_oe_rd_minM) begin if (set_rd_minM='0') then d_rd_minM <= not_oe_rd_minM ; else d_rd_minM <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_minM, PCLOCK_I) begin if (rst_rd_minM='1') then not_oe_rd_minM <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_minM <= d_rd_minM ; end if; end process; -- -------------------------------------------------- -- "output enable" to read ACCEPT3L f/f (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx1 00xx = 10010 hex -- -- -------------------------------------------------- cs_rd_accept3l <= (not ADDR_I(17)) and ADDR_I(16) and ADDR_I(4) and (not ADDR_I(3)) and (not ADDR_I(2)) ; rst_rd_accept3l <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_accept3l and (not PCLOCK_I) ) ; set_rd_accept3l <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_accept3l, not_oe_rd_accept3l) begin if (set_rd_accept3l='0') then d_rd_accept3l <= not_oe_rd_accept3l ; else d_rd_accept3l <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_accept3l, PCLOCK_I) begin if (rst_rd_accept3l='1') then not_oe_rd_accept3l <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_accept3l <= d_rd_accept3l ; end if; end process; -- -------------------------------------------------- ----- -- "output enable" to read CONV1LINE_DONE register (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx1 01xx = 10014 hex -- -- -------------------------------------------------------- cs_rd_conv1line_done <= (not ADDR_I(17)) and ADDR_I(16) and ADDR_I(4) and (not ADDR_I(3)) and ADDR_I(2) ; rst_rd_conv1line_done <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_conv1line_done and (not PCLOCK_I) ) ; set_rd_conv1line_done <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_conv1line_done, not_oe_rd_conv1line_done) begin if (set_rd_conv1line_done='0') then d_rd_conv1line_done <= not_oe_rd_conv1line_done ; else d_rd_conv1line_done <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_conv1line_done, PCLOCK_I) begin if (rst_rd_conv1line_done='1') then not_oe_rd_conv1line_done <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_conv1line_done <= d_rd_conv1line_done ; end if; end process; -- ----------------------------------------------------- -- "output enable" to read CONVOL_DONE register (/OE) -- -- ADDR[17:0] = 01 xxxx xxxx xxx1 10xx = 10018 hex -- -- ----------------------------------------------------- cs_rd_convol_done <= (not ADDR_I(17)) and ADDR_I(16) and ADDR_I(4) and ADDR_I(3) and (not ADDR_I(2)) ; rst_rd_convol_done <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and cs_rd_convol_done and (not PCLOCK_I) ) ; set_rd_convol_done <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_rd_convol_done, not_oe_rd_convol_done) begin if (set_rd_convol_done='0') then d_rd_convol_done <= not_oe_rd_convol_done ; else d_rd_convol_done <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rst_rd_convol_done, PCLOCK_I) begin if (rst_rd_convol_done='1') then not_oe_rd_convol_done <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then not_oe_rd_convol_done <= d_rd_convol_done ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to LINES_IN ram (LOAD) -- -- ADDR[17:0] = 00 0xxx xxxx xxxx xxxx = (00000 hex + RAM offset) -- -- ----------------------------------------------------------------- cs_wr_lines_in <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(15)); set_wr_lines_in <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_lines_in and (not PCLOCK_I) ; rst_wr_lines_in <= ADDR_VLD_I or delayed_reset ; load_wr_lines_in <= q1_wr_lines_in and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_lines_in, q1_wr_lines_in) begin if (set_wr_lines_in='1') then d1_wr_lines_in <= '1'; else d1_wr_lines_in <= q1_wr_lines_in ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_lines_in, PCLOCK_I) begin if (rst_wr_lines_in='1') then -- reset q1_wr_lines_in <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_lines_in <= d1_wr_lines_in ; end if; end process; -- -------------------------------------------------------- -- "write enable" to write to READ_DONE flip-flop (LOAD) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 00xx = 10000 hex -- -- -------------------------------------------------------- cs_wr_read_done <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and (not ADDR_I(3)) and (not ADDR_I(2)); set_wr_read_done <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_read_done and (not PCLOCK_I) ; rst_wr_read_done <= ADDR_VLD_I or delayed_reset ; load_wr_read_done <= q1_wr_read_done and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_read_done, q1_wr_read_done) begin if (set_wr_read_done='1') then d1_wr_read_done <= '1'; else d1_wr_read_done <= q1_wr_read_done ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_read_done, PCLOCK_I) begin if (rst_wr_read_done='1') then -- reset q1_wr_read_done <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_read_done <= d1_wr_read_done ; end if; end process; -- -------------------------------------------------------- -- "write enable" to write to WRITE_DONE flip-flop (LOAD) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 01xx = 10004 hex -- -- -------------------------------------------------------- cs_wr_write_done <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and (not ADDR_I(3)) and ADDR_I(2); set_wr_write_done <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_write_done and (not PCLOCK_I) ; rst_wr_write_done <= ADDR_VLD_I or delayed_reset ; load_wr_write_done <= q1_wr_write_done and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_write_done, q1_wr_write_done) begin if (set_wr_write_done='1') then d1_wr_write_done <= '1'; else d1_wr_write_done <= q1_wr_write_done ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_write_done, PCLOCK_I) begin if (rst_wr_write_done='1') then -- reset q1_wr_write_done <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_write_done <= d1_wr_write_done ; end if; end process; -- -------------------------------------------------------- -- "write enable" to write to WR_FINISHED flip-flop (LOAD) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 10xx = 10008 hex -- -- -------------------------------------------------------- cs_wr_wr_finished <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and ADDR_I(3) and (not ADDR_I(2)); set_wr_wr_finished <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_wr_finished and (not PCLOCK_I) ; rst_wr_wr_finished <= ADDR_VLD_I or delayed_reset ; load_wr_wr_finished <= q1_wr_wr_finished and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_wr_finished, q1_wr_wr_finished) begin if (set_wr_wr_finished='1') then d1_wr_wr_finished <= '1'; else d1_wr_wr_finished <= q1_wr_wr_finished ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_wr_finished, PCLOCK_I) begin if (rst_wr_wr_finished='1') then -- reset q1_wr_wr_finished <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_wr_finished <= d1_wr_wr_finished ; end if; end process; -- -------------------------------------------------------- -- "write enable" to write to WRITTEN3L flip-flop (LOAD) -- -- ADDR[17:0] = 01 xxxx xxxx xxx0 11xx = 1000C hex -- -- -------------------------------------------------------- cs_wr_written3l <= (not ADDR_I(17)) and ADDR_I(16) and (not ADDR_I(4)) and ADDR_I(3) and ADDR_I(2); set_wr_written3l <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_written3l and (not PCLOCK_I) ; rst_wr_written3l <= ADDR_VLD_I or delayed_reset ; load_wr_written3l <= q1_wr_written3l and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_written3l, q1_wr_written3l) begin if (set_wr_written3l='1') then d1_wr_written3l <= '1'; else d1_wr_written3l <= q1_wr_written3l ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_written3l, PCLOCK_I) begin if (rst_wr_written3l='1') then -- reset q1_wr_written3l <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_written3l <= d1_wr_written3l ; end if; end process; -- -------------------------------------------------------- -- "write enable" to write to RESET_FF flip-flop (LOAD) -- -- ADDR[17:0] = 01 xxxx xxxx xxx1 00xx = 10010 hex -- -- -------------------------------------------------------- cs_wr_reset_ff <= (not ADDR_I(17)) and ADDR_I(16) and ADDR_I(4) and (not ADDR_I(3)) and (not ADDR_I(2)); set_wr_reset_ff <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_reset_ff and (not PCLOCK_I) ; rst_wr_reset_ff <= ADDR_VLD_I or delayed_reset ; load_wr_reset_ff <= q1_wr_reset_ff and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_reset_ff, q1_wr_reset_ff) begin if (set_wr_reset_ff='1') then d1_wr_reset_ff <= '1'; else d1_wr_reset_ff <= q1_wr_reset_ff ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_reset_ff, PCLOCK_I) begin if (rst_wr_reset_ff='1') then -- reset q1_wr_reset_ff <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_reset_ff <= d1_wr_reset_ff ; end if; end process; -- -------------------------------------------------------- -- "write enable" to write to START_FSM flip-flop (LOAD) -- -- ADDR[17:0] = 01 xxxx xxxx xxx1 01xx = 10014 hex -- -- -------------------------------------------------------- cs_wr_start_fsm <= (not ADDR_I(17)) and ADDR_I(16) and ADDR_I(4) and (not ADDR_I(3)) and ADDR_I(2); set_wr_start_fsm <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and cs_wr_start_fsm and (not PCLOCK_I) ; rst_wr_start_fsm <= ADDR_VLD_I or delayed_reset ; load_wr_start_fsm <= q1_wr_start_fsm and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (set_wr_start_fsm, q1_wr_start_fsm) begin if (set_wr_start_fsm='1') then d1_wr_start_fsm <= '1'; else d1_wr_start_fsm <= q1_wr_start_fsm ; end if; end process; -- flip-flop D with asynchronous reset process (rst_wr_start_fsm, PCLOCK_I) begin if (rst_wr_start_fsm='1') then -- reset q1_wr_start_fsm <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1_wr_start_fsm <= d1_wr_start_fsm ; end if; end process; -- =================================================================== end ffs_e_muxes;