-- ======================================================================= -- Author: Antonio Esteves, GEC-DI-UM. -- File: interface.vhd -- Date: 13 August 2000 -- -- Component allocated to an FPGA for the hw/sw convolution implementation. -- Synthesizable version. -- -- MODULE DEFINING THE INTERFACE WITH THE FPGA. -- ======================================================================= library IEEE; use IEEE.std_logic_1164.all; -- -------------------------------------------------------------- -- FPGA INTERFACE ENTITY -- -- * PINS NOT USED MUST BE COMMENTED in the entity declaration and in the -- buffers instantiation section. -- -- * THE inout PINS CAN BE USED AS INPUT (in) OR OUTPUT (out). In -- such case: -- -- 1) if using a INOUT pin as IN: -- -- (i) replace 'inout' by 'in' in the adequate line of the section -- "signals connecting the fpga to the exterior" of the entity -- declaration; -- (ii) comment the the adequate line, using 'in', in the section -- "signals connecting to the rest of the fpga logic" of the -- entity declaration; -- (iii) comment the adequate line with 'OBUFT' in the buffers -- instantiation section; -- (iv) comment the adequate line in the section "signals to control -- tri-state buffers of bi-direccional pins" of the entity -- declaration (a signal with a name like 'not_oe_xx'). -- -- 2) if using INOUT pin as OUT: -- -- (i) replace 'inout' by 'out' in the adequate line in the section -- "signals connecting the fpga to the exterior" of the entity -- declaration; -- (ii) comment the the adequate line, using 'out', in the section -- "signals connecting to the rest of the fpga logic" of the -- entity declaration; -- (iii) comment the adequate line with 'IBUF' in the buffers -- instantiation section; -- (iii) replace the adequate line with 'OBUFT', in the buffers -- instantiation section, for a line with 'OBUF', like -- explained in the next situation: -- -- (before) PO_#: OBUFT port map (I => SIGNAL_O(#), -- T=> not_oe_xxx, O => SIGNAL(#)); -- (after) PO_#: OBUF port map (I => SIGNAL_O(#), -- O => SIGNAL(#)); -- -- (iv) comment the adequate line in the section "signals to control -- tri-state buffers of bi-direccional pins" of the entity -- declaration (a signal with a name like 'not_oe_xx'). entity fpga_interface is port ( -- ---------------------------------------------------------- -- signals connecting the fpga to the exterior NOTWR : in std_logic ; NOTRD : in std_logic ; RESET : in std_logic ; PCLOCK : in std_logic ; SCLOCK : in std_logic ; BASE_HIT0 : in std_logic ; ADDR_VLD : in std_logic ; S_DATA_VLD : in std_logic ; PCI_CMD7 : in std_logic ; PCI_CMD6 : in std_logic ; S_CBE : in std_logic ; ADDR : in std_logic_vector(17 downto 0) ; DATA : inout std_logic_vector( 7 downto 0) ; -- ** INOUT S_SRC_EN : in std_logic ; S_DATA : in std_logic ; DATA_UP : inout std_logic_vector(32 downto 0) ; -- ** INOUT DATA_DWN : inout std_logic_vector(32 downto 0) ; -- ** INOUT CONNECTOR : inout std_logic_vector(15 downto 0) ; -- ** INOUT DATA2CPLD : inout std_logic_vector( 7 downto 0) ; -- ** INOUT CLK_CPLD : in std_logic_vector( 1 downto 0) ; CLK_DWN_OUT : out std_logic ; CLK_DWN_IN : in std_logic ; CLK_UP_OUT : out std_logic ; CLK_UP_IN : in std_logic ; GENERICO : inout std_logic_vector( 2 downto 1); -- ** INOUT -- ---------------------------------------------------------- -- signals connecting to the rest of the fpga logic NOTWR_I : out std_logic ; NOTRD_I : out std_logic ; RESET_I : out std_logic ; PCLOCK_I : out std_logic ; SCLOCK_I : out std_logic ; BASE_HIT0_I : out std_logic ; ADDR_VLD_I : out std_logic ; S_DATA_VLD_I : out std_logic ; PCI_CMD7_I : out std_logic ; PCI_CMD6_I : out std_logic ; S_CBE_I : out std_logic ; ADDR_I : out std_logic_vector(17 downto 0) ; DATA_I : out std_logic_vector( 7 downto 0) ; -- ** INOUT DATA_O : in std_logic_vector( 7 downto 0) ; -- ** INOUT S_SRC_EN_I : out std_logic ; S_DATA_I : out std_logic ; DATA_UP_O : in std_logic_vector(32 downto 0) ; -- ** INOUT DATA_UP_I : out std_logic_vector(32 downto 0) ; -- ** INOUT CONNECTOR_O : in std_logic_vector(15 downto 0) ; -- ** INOUT CONNECTOR_I : out std_logic_vector(15 downto 0) ; -- ** INOUT DATA_DWN_O : in std_logic_vector(32 downto 0) ; -- ** INOUT DATA_DWN_I : out std_logic_vector(32 downto 0) ; -- ** INOUT DATA2CPLD_O : in std_logic_vector( 7 downto 0) ; -- ** INOUT DATA2CPLD_I : out std_logic_vector( 7 downto 0) ; -- ** INOUT CLK_CPLD_I : out std_logic_vector( 1 downto 0) ; CLK_DWN_OUT_O : in std_logic ; CLK_DWN_IN_I : out std_logic ; CLK_UP_OUT_O : in std_logic ; CLK_UP_IN_I : out std_logic ; GENERICO_O : in std_logic_vector( 2 downto 1) ; -- ** INOUT GENERICO_I : out std_logic_vector( 2 downto 1) ; -- ** INOUT -- ---------------------------------------------------------- -- signals to control tri-state buffers of bi-direccional pins not_oe_d : in std_logic; not_oe_d2c : in std_logic; not_oe_dup : in std_logic; not_oe_ddwn : in std_logic; not_oe_gen : in std_logic; not_oe_conn : in std_logic ); end fpga_interface ; -- end of FPGA INTERFACE ENTITY -- -------------------------------------------------------------- architecture buffers of fpga_interface is -- ------------------------------------------------------------- -- VHDL Code for Instantiating BSCAN in the XC4000/E/X/XL component bscan port(tdi, tms, tck: in std_ulogic; tdo: out std_ulogic); end component; component tck port ( i : out std_ulogic ); end component; component tdi port ( i : out std_ulogic ); end component; component tms port ( i : out std_ulogic ); end component; component tdo port ( o : in std_ulogic ); end component; -- End of VHDL Code for Instantiating BSCAN in the XC4000/E/X/XL -- ------------------------------------------------------------- -- IBUF declaration component IBUF port(I: in std_logic; O: out std_logic); end component; -- OBUF declaration component OBUF port(I: in std_logic; O: out std_logic); end component; -- OBUFT declaration component OBUFT port(I: in std_logic; T: in std_logic; O: out std_logic); end component; -- CLOCK buffer declaration component BUFGLS port(O : out std_logic;I : in std_logic); end component; -- ------------------------------------------------------------- -- signals used to insert CLOCK buffers signal PCLOCK_I1 : std_logic ; signal SCLOCK_I1 : std_logic ; -- ------------------------------------------------------------- -- VHDL Code for Instantiating BSCAN in the XC4000/E/X/XL signal tck_net : std_ulogic ; signal tdi_net : std_ulogic ; signal tms_net : std_ulogic ; signal tdo_net : std_ulogic ; -- End of VHDL Code for Instantiating BSCAN in the XC4000/E/X/XL -- ------------------------------------------------------------- begin -- ------------------------------------------------------------ -- VHDL Code for Instantiating BSCAN in the XC4000/E/X/XL u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net); u2: tck port map (i=>tck_net); u3: tdi port map (i=>tdi_net); u4: tms port map (i=>tms_net); u5: tdo port map (o=>tdo_net); -- End of VHDL Code for Instantiating BSCAN in the XC4000/E/X/XL -- ------------------------------------------------------------ -- ------------------------------------------------------------ -- CLOCK buffers PCLK_BUF: BUFGLS port map (I => PCLOCK_I1 , O => PCLOCK_I ) ; SCLK_BUF: BUFGLS port map (I => SCLOCK_I1 , O => SCLOCK_I ) ; -- ------------------------------------------------------------- -- IBUF instantiation for input pins PIN_NOTWR: IBUF port map (I => NOTWR , O => NOTWR_I ) ; PIN_NOTRD: IBUF port map (I => NOTRD , O => NOTRD_I ) ; PIN_RESET: IBUF port map (I => RESET , O => RESET_I ) ; PIN_PCLOCK: IBUF port map (I => PCLOCK , O => PCLOCK_I1 ) ; PIN_SCLOCK: IBUF port map (I => SCLOCK , O => SCLOCK_I1 ) ; PIN_BHIT0: IBUF port map (I => BASE_HIT0 , O => BASE_HIT0_I ) ; PIN_AVLD: IBUF port map (I => ADDR_VLD , O => ADDR_VLD_I ) ; PIN_DVLD: IBUF port map (I => S_DATA_VLD , O => S_DATA_VLD_I ) ; PIN_CMD7: IBUF port map (I => PCI_CMD7 , O => PCI_CMD7_I ) ; PIN_CMD6: IBUF port map (I => PCI_CMD6 , O => PCI_CMD6_I ) ; PIN_SCBE: IBUF port map (I => S_CBE , O => S_CBE_I ) ; PIN_SRCEN: IBUF port map (I => S_SRC_EN , O => S_SRC_EN_I ) ; PIN_SDATA: IBUF port map (I => S_DATA , O => S_DATA_I ) ; PIN_ADDR0: IBUF port map (I => ADDR(0) , O => ADDR_I(0) ) ; PIN_ADDR1: IBUF port map (I => ADDR(1) , O => ADDR_I(1) ) ; PIN_ADDR2: IBUF port map (I => ADDR(2) , O => ADDR_I(2) ) ; PIN_ADDR3: IBUF port map (I => ADDR(3) , O => ADDR_I(3) ) ; PIN_ADDR4: IBUF port map (I => ADDR(4) , O => ADDR_I(4) ) ; PIN_ADDR5: IBUF port map (I => ADDR(5) , O => ADDR_I(5) ) ; PIN_ADDR6: IBUF port map (I => ADDR(6) , O => ADDR_I(6) ) ; PIN_ADDR7: IBUF port map (I => ADDR(7) , O => ADDR_I(7) ) ; PIN_ADDR8: IBUF port map (I => ADDR(8) , O => ADDR_I(8) ) ; PIN_ADDR9: IBUF port map (I => ADDR(9) , O => ADDR_I(9) ) ; PIN_ADDR10: IBUF port map (I => ADDR(10) , O => ADDR_I(10) ) ; PIN_ADDR11: IBUF port map (I => ADDR(11) , O => ADDR_I(11) ) ; PIN_ADDR12: IBUF port map (I => ADDR(12) , O => ADDR_I(12) ) ; PIN_ADDR13: IBUF port map (I => ADDR(13) , O => ADDR_I(13) ) ; PIN_ADDR14: IBUF port map (I => ADDR(14) , O => ADDR_I(14) ) ; PIN_ADDR15: IBUF port map (I => ADDR(15) , O => ADDR_I(15) ) ; PIN_ADDR16: IBUF port map (I => ADDR(16) , O => ADDR_I(16) ) ; PIN_ADDR17: IBUF port map (I => ADDR(17) , O => ADDR_I(17) ) ; P_C_CPLD0: IBUF port map (I => CLK_CPLD(0) , O => CLK_CPLD_I(0) ) ; P_C_CPLD1: IBUF port map (I => CLK_CPLD(1) , O => CLK_CPLD_I(1) ) ; P_C_UP_IN: IBUF port map (I => CLK_UP_IN , O => CLK_UP_IN_I ) ; P_C_DWN_IN: IBUF port map (I => CLK_DWN_IN , O => CLK_DWN_IN_I ) ; -- ------------------------------------------------------------- -- OBUF instantiation for output pins P_C_UP_OUT: OBUF port map (I => CLK_UP_OUT_O , O => CLK_UP_OUT ) ; P_C_DWN_OUT: OBUF port map (I => CLK_DWN_OUT_O , O => CLK_DWN_OUT ) ; -- ------------------------------------------------------------- -- IBUF and OBUFT instantiation for bi-directional pins -- DATA2CPLD(7:0) CAN BE BI-DIRECTIONAL PINS PI_D2CPLD0: IBUF port map (I => DATA2CPLD(0) , O => DATA2CPLD_I(0) ) ; PI_D2CPLD1: IBUF port map (I => DATA2CPLD(1) , O => DATA2CPLD_I(1) ) ; PI_D2CPLD2: IBUF port map (I => DATA2CPLD(2) , O => DATA2CPLD_I(2) ) ; PI_D2CPLD3: IBUF port map (I => DATA2CPLD(3) , O => DATA2CPLD_I(3) ) ; PI_D2CPLD4: IBUF port map (I => DATA2CPLD(4) , O => DATA2CPLD_I(4) ) ; PI_D2CPLD5: IBUF port map (I => DATA2CPLD(5) , O => DATA2CPLD_I(5) ) ; PI_D2CPLD6: IBUF port map (I => DATA2CPLD(6) , O => DATA2CPLD_I(6) ) ; PI_D2CPLD7: IBUF port map (I => DATA2CPLD(7) , O => DATA2CPLD_I(7) ) ; PO_D2CPLD0: OBUFT port map (I => DATA2CPLD_o(0), T=> not_oe_d2c, O => DATA2CPLD(0)) ; PO_D2CPLD1: OBUFT port map (I => DATA2CPLD_o(1), T=> not_oe_d2c, O => DATA2CPLD(1)) ; PO_D2CPLD2: OBUFT port map (I => DATA2CPLD_o(2), T=> not_oe_d2c, O => DATA2CPLD(2)) ; PO_D2CPLD3: OBUFT port map (I => DATA2CPLD_o(3), T=> not_oe_d2c, O => DATA2CPLD(3)) ; PO_D2CPLD4: OBUFT port map (I => DATA2CPLD_o(4), T=> not_oe_d2c, O => DATA2CPLD(4)) ; PO_D2CPLD5: OBUFT port map (I => DATA2CPLD_o(5), T=> not_oe_d2c, O => DATA2CPLD(5)) ; PO_D2CPLD6: OBUFT port map (I => DATA2CPLD_o(6), T=> not_oe_d2c, O => DATA2CPLD(6)) ; PO_D2CPLD7: OBUFT port map (I => DATA2CPLD_o(7), T=> not_oe_d2c, O => DATA2CPLD(7)) ; -- DATA(7:0) CAN BE BI-DIRECTIONAL PINS DATA_IBUF0: IBUF port map (I => DATA(0), O => data_I(0) ) ; DATA_IBUF1: IBUF port map (I => DATA(1), O => data_I(1) ) ; DATA_IBUF2: IBUF port map (I => DATA(2), O => data_I(2) ) ; DATA_IBUF3: IBUF port map (I => DATA(3), O => data_I(3) ) ; DATA_IBUF4: IBUF port map (I => DATA(4), O => data_I(4) ) ; DATA_IBUF5: IBUF port map (I => DATA(5), O => data_I(5) ) ; DATA_IBUF6: IBUF port map (I => DATA(6), O => data_I(6) ) ; DATA_IBUF7: IBUF port map (I => DATA(7), O => data_I(7) ) ; DATA_OBUF0: OBUFT port map (I => data_o(0), T=> not_oe_d, O => DATA(0)) ; DATA_OBUF1: OBUFT port map (I => data_o(1), T=> not_oe_d, O => DATA(1)) ; DATA_OBUF2: OBUFT port map (I => data_o(2), T=> not_oe_d, O => DATA(2)) ; DATA_OBUF3: OBUFT port map (I => data_o(3), T=> not_oe_d, O => DATA(3)) ; DATA_OBUF4: OBUFT port map (I => data_o(4), T=> not_oe_d, O => DATA(4)) ; DATA_OBUF5: OBUFT port map (I => data_o(5), T=> not_oe_d, O => DATA(5)) ; DATA_OBUF6: OBUFT port map (I => data_o(6), T=> not_oe_d, O => DATA(6)) ; DATA_OBUF7: OBUFT port map (I => data_o(7), T=> not_oe_d, O => DATA(7)) ; -- DATA_UP(32:0) CAN BE BI-DIRECTIONAL PINS PI_DATAUP0: IBUF port map (I => DATA_UP(0), O => DATA_UP_I(0) ) ; PI_DATAUP1: IBUF port map (I => DATA_UP(1), O => DATA_UP_I(1) ) ; PI_DATAUP2: IBUF port map (I => DATA_UP(2), O => DATA_UP_I(2) ) ; PI_DATAUP3: IBUF port map (I => DATA_UP(3), O => DATA_UP_I(3) ) ; PI_DATAUP4: IBUF port map (I => DATA_UP(4), O => DATA_UP_I(4) ) ; PI_DATAUP5: IBUF port map (I => DATA_UP(5), O => DATA_UP_I(5) ) ; PI_DATAUP6: IBUF port map (I => DATA_UP(6), O => DATA_UP_I(6) ) ; PI_DATAUP7: IBUF port map (I => DATA_UP(7), O => DATA_UP_I(7) ) ; PI_DATAUP8: IBUF port map (I => DATA_UP(8), O => DATA_UP_I(8) ) ; PI_DATAUP9: IBUF port map (I => DATA_UP(9), O => DATA_UP_I(9) ) ; PI_DATAUP10: IBUF port map (I => DATA_UP(10), O => DATA_UP_I(10) ) ; PI_DATAUP11: IBUF port map (I => DATA_UP(11), O => DATA_UP_I(11) ) ; PI_DATAUP12: IBUF port map (I => DATA_UP(12), O => DATA_UP_I(12) ) ; PI_DATAUP13: IBUF port map (I => DATA_UP(13), O => DATA_UP_I(13) ) ; PI_DATAUP14: IBUF port map (I => DATA_UP(14), O => DATA_UP_I(14) ) ; PI_DATAUP15: IBUF port map (I => DATA_UP(15), O => DATA_UP_I(15) ) ; PI_DATAUP16: IBUF port map (I => DATA_UP(16), O => DATA_UP_I(16) ) ; PI_DATAUP17: IBUF port map (I => DATA_UP(17), O => DATA_UP_I(17) ) ; PI_DATAUP18: IBUF port map (I => DATA_UP(18), O => DATA_UP_I(18) ) ; PI_DATAUP19: IBUF port map (I => DATA_UP(19), O => DATA_UP_I(19) ) ; PI_DATAUP20: IBUF port map (I => DATA_UP(20), O => DATA_UP_I(20) ) ; PI_DATAUP21: IBUF port map (I => DATA_UP(21), O => DATA_UP_I(21) ) ; PI_DATAUP22: IBUF port map (I => DATA_UP(22), O => DATA_UP_I(22) ) ; PI_DATAUP23: IBUF port map (I => DATA_UP(23), O => DATA_UP_I(23) ) ; PI_DATAUP24: IBUF port map (I => DATA_UP(24), O => DATA_UP_I(24) ) ; PI_DATAUP25: IBUF port map (I => DATA_UP(25), O => DATA_UP_I(25) ) ; PI_DATAUP26: IBUF port map (I => DATA_UP(26), O => DATA_UP_I(26) ) ; PI_DATAUP27: IBUF port map (I => DATA_UP(27), O => DATA_UP_I(27) ) ; PI_DATAUP28: IBUF port map (I => DATA_UP(28), O => DATA_UP_I(28) ) ; PI_DATAUP29: IBUF port map (I => DATA_UP(29), O => DATA_UP_I(29) ) ; PI_DATAUP30: IBUF port map (I => DATA_UP(30), O => DATA_UP_I(30) ) ; PI_DATAUP31: IBUF port map (I => DATA_UP(31), O => DATA_UP_I(31) ) ; PI_DATAUP32: IBUF port map (I => DATA_UP(32), O => DATA_UP_I(32) ) ; PO_DATAUP0: OBUFT port map (I => DATA_UP_O(0) , T=> not_oe_dup, O => DATA_UP(0) ) ; PO_DATAUP1: OBUFT port map (I => DATA_UP_O(1) , T=> not_oe_dup, O => DATA_UP(1) ) ; PO_DATAUP2: OBUFT port map (I => DATA_UP_O(2) , T=> not_oe_dup, O => DATA_UP(2) ) ; PO_DATAUP3: OBUFT port map (I => DATA_UP_O(3) , T=> not_oe_dup, O => DATA_UP(3) ) ; PO_DATAUP4: OBUFT port map (I => DATA_UP_O(4) , T=> not_oe_dup, O => DATA_UP(4) ) ; PO_DATAUP5: OBUFT port map (I => DATA_UP_O(5) , T=> not_oe_dup, O => DATA_UP(5) ) ; PO_DATAUP6: OBUFT port map (I => DATA_UP_O(6) , T=> not_oe_dup, O => DATA_UP(6) ) ; PO_DATAUP7: OBUFT port map (I => DATA_UP_O(7) , T=> not_oe_dup, O => DATA_UP(7) ) ; PO_DATAUP8: OBUFT port map (I => DATA_UP_O(8) , T=> not_oe_dup, O => DATA_UP(8) ) ; PO_DATAUP9: OBUFT port map (I => DATA_UP_O(9) , T=> not_oe_dup, O => DATA_UP(9) ) ; PO_DATAUP10: OBUFT port map (I => DATA_UP_O(10) , T=> not_oe_dup, O => DATA_UP(10) ) ; PO_DATAUP11: OBUFT port map (I => DATA_UP_O(11) , T=> not_oe_dup, O => DATA_UP(11) ) ; PO_DATAUP12: OBUFT port map (I => DATA_UP_O(12) , T=> not_oe_dup, O => DATA_UP(12) ) ; PO_DATAUP13: OBUFT port map (I => DATA_UP_O(13) , T=> not_oe_dup, O => DATA_UP(13) ) ; PO_DATAUP14: OBUFT port map (I => DATA_UP_O(14) , T=> not_oe_dup, O => DATA_UP(14) ) ; PO_DATAUP15: OBUFT port map (I => DATA_UP_O(15) , T=> not_oe_dup, O => DATA_UP(15) ) ; PO_DATAUP16: OBUFT port map (I => DATA_UP_O(16) , T=> not_oe_dup, O => DATA_UP(16) ) ; PO_DATAUP17: OBUFT port map (I => DATA_UP_O(17) , T=> not_oe_dup, O => DATA_UP(17) ) ; PO_DATAUP18: OBUFT port map (I => DATA_UP_O(18) , T=> not_oe_dup, O => DATA_UP(18) ) ; PO_DATAUP19: OBUFT port map (I => DATA_UP_O(19) , T=> not_oe_dup, O => DATA_UP(19) ) ; PO_DATAUP20: OBUFT port map (I => DATA_UP_O(20) , T=> not_oe_dup, O => DATA_UP(20) ) ; PO_DATAUP21: OBUFT port map (I => DATA_UP_O(21) , T=> not_oe_dup, O => DATA_UP(21) ) ; PO_DATAUP22: OBUFT port map (I => DATA_UP_O(22) , T=> not_oe_dup, O => DATA_UP(22) ) ; PO_DATAUP23: OBUFT port map (I => DATA_UP_O(23) , T=> not_oe_dup, O => DATA_UP(23) ) ; PO_DATAUP24: OBUFT port map (I => DATA_UP_O(24) , T=> not_oe_dup, O => DATA_UP(24) ) ; PO_DATAUP25: OBUFT port map (I => DATA_UP_O(25) , T=> not_oe_dup, O => DATA_UP(25) ) ; PO_DATAUP26: OBUFT port map (I => DATA_UP_O(26) , T=> not_oe_dup, O => DATA_UP(26) ) ; PO_DATAUP27: OBUFT port map (I => DATA_UP_O(27) , T=> not_oe_dup, O => DATA_UP(27) ) ; PO_DATAUP28: OBUFT port map (I => DATA_UP_O(28) , T=> not_oe_dup, O => DATA_UP(28) ) ; PO_DATAUP29: OBUFT port map (I => DATA_UP_O(29) , T=> not_oe_dup, O => DATA_UP(29) ) ; PO_DATAUP30: OBUFT port map (I => DATA_UP_O(30) , T=> not_oe_dup, O => DATA_UP(30) ) ; PO_DATAUP31: OBUFT port map (I => DATA_UP_O(31) , T=> not_oe_dup, O => DATA_UP(31) ) ; PO_DATAUP32: OBUFT port map (I => DATA_UP_O(32) , T=> not_oe_dup, O => DATA_UP(32) ) ; -- DATA_DWN(32:0) CAN BE BI-DIRECTIONAL PINS PI_DATADWN0: IBUF port map (I => DATA_DWN(0), O => DATA_DWN_I(0) ); PI_DATADWN1: IBUF port map (I => DATA_DWN(1), O => DATA_DWN_I(1) ); PI_DATADWN2: IBUF port map (I => DATA_DWN(2), O => DATA_DWN_I(2) ); PI_DATADWN3: IBUF port map (I => DATA_DWN(3), O => DATA_DWN_I(3) ); PI_DATADWN4: IBUF port map (I => DATA_DWN(4), O => DATA_DWN_I(4) ); PI_DATADWN5: IBUF port map (I => DATA_DWN(5), O => DATA_DWN_I(5) ); PI_DATADWN6: IBUF port map (I => DATA_DWN(6), O => DATA_DWN_I(6) ); PI_DATADWN7: IBUF port map (I => DATA_DWN(7), O => DATA_DWN_I(7) ); PI_DATADWN8: IBUF port map (I => DATA_DWN(8), O => DATA_DWN_I(8) ); PI_DATADWN9: IBUF port map (I => DATA_DWN(9), O => DATA_DWN_I(9) ); PI_DATADWN10: IBUF port map (I => DATA_DWN(10), O => DATA_DWN_I(10) ); PI_DATADWN11: IBUF port map (I => DATA_DWN(11), O => DATA_DWN_I(11) ); PI_DATADWN12: IBUF port map (I => DATA_DWN(12), O => DATA_DWN_I(12) ); PI_DATADWN13: IBUF port map (I => DATA_DWN(13), O => DATA_DWN_I(13) ); PI_DATADWN14: IBUF port map (I => DATA_DWN(14), O => DATA_DWN_I(14) ); PI_DATADWN15: IBUF port map (I => DATA_DWN(15), O => DATA_DWN_I(15) ); PI_DATADWN16: IBUF port map (I => DATA_DWN(16), O => DATA_DWN_I(16) ); PI_DATADWN17: IBUF port map (I => DATA_DWN(17), O => DATA_DWN_I(17) ); PI_DATADWN18: IBUF port map (I => DATA_DWN(18), O => DATA_DWN_I(18) ); PI_DATADWN19: IBUF port map (I => DATA_DWN(19), O => DATA_DWN_I(19) ); PI_DATADWN20: IBUF port map (I => DATA_DWN(20), O => DATA_DWN_I(20) ); PI_DATADWN21: IBUF port map (I => DATA_DWN(21), O => DATA_DWN_I(21) ); PI_DATADWN22: IBUF port map (I => DATA_DWN(22), O => DATA_DWN_I(22) ); PI_DATADWN23: IBUF port map (I => DATA_DWN(23), O => DATA_DWN_I(23) ); PI_DATADWN24: IBUF port map (I => DATA_DWN(24), O => DATA_DWN_I(24) ); PI_DATADWN25: IBUF port map (I => DATA_DWN(25), O => DATA_DWN_I(25) ); PI_DATADWN26: IBUF port map (I => DATA_DWN(26), O => DATA_DWN_I(26) ); PI_DATADWN27: IBUF port map (I => DATA_DWN(27), O => DATA_DWN_I(27) ); PI_DATADWN28: IBUF port map (I => DATA_DWN(28), O => DATA_DWN_I(28) ); PI_DATADWN29: IBUF port map (I => DATA_DWN(29), O => DATA_DWN_I(29) ); PI_DATADWN30: IBUF port map (I => DATA_DWN(30), O => DATA_DWN_I(30) ); PI_DATADWN31: IBUF port map (I => DATA_DWN(31), O => DATA_DWN_I(31) ); PI_DATADWN32: IBUF port map (I => DATA_DWN(32), O => DATA_DWN_I(32) ); PO_DATADWN0: OBUFT port map (I => DATA_DWN_O(0) , T=> not_oe_ddwn, O => DATA_DWN(0) ) ; PO_DATADWN1: OBUFT port map (I => DATA_DWN_O(1) , T=> not_oe_ddwn, O => DATA_DWN(1) ) ; PO_DATADWN2: OBUFT port map (I => DATA_DWN_O(2) , T=> not_oe_ddwn, O => DATA_DWN(2) ) ; PO_DATADWN3: OBUFT port map (I => DATA_DWN_O(3) , T=> not_oe_ddwn, O => DATA_DWN(3) ) ; PO_DATADWN4: OBUFT port map (I => DATA_DWN_O(4) , T=> not_oe_ddwn, O => DATA_DWN(4) ) ; PO_DATADWN5: OBUFT port map (I => DATA_DWN_O(5) , T=> not_oe_ddwn, O => DATA_DWN(5) ) ; PO_DATADWN6: OBUFT port map (I => DATA_DWN_O(6) , T=> not_oe_ddwn, O => DATA_DWN(6) ) ; PO_DATADWN7: OBUFT port map (I => DATA_DWN_O(7) , T=> not_oe_ddwn, O => DATA_DWN(7) ) ; PO_DATADWN8: OBUFT port map (I => DATA_DWN_O(8) , T=> not_oe_ddwn, O => DATA_DWN(8) ) ; PO_DATADWN9: OBUFT port map (I => DATA_DWN_O(9) , T=> not_oe_ddwn, O => DATA_DWN(9) ) ; PO_DATADWN10: OBUFT port map (I => DATA_DWN_O(10) , T=> not_oe_ddwn, O => DATA_DWN(10) ) ; PO_DATADWN11: OBUFT port map (I => DATA_DWN_O(11) , T=> not_oe_ddwn, O => DATA_DWN(11) ) ; PO_DATADWN12: OBUFT port map (I => DATA_DWN_O(12) , T=> not_oe_ddwn, O => DATA_DWN(12) ) ; PO_DATADWN13: OBUFT port map (I => DATA_DWN_O(13) , T=> not_oe_ddwn, O => DATA_DWN(13) ) ; PO_DATADWN14: OBUFT port map (I => DATA_DWN_O(14) , T=> not_oe_ddwn, O => DATA_DWN(14) ) ; PO_DATADWN15: OBUFT port map (I => DATA_DWN_O(15) , T=> not_oe_ddwn, O => DATA_DWN(15) ) ; PO_DATADWN16: OBUFT port map (I => DATA_DWN_O(16) , T=> not_oe_ddwn, O => DATA_DWN(16) ) ; PO_DATADWN17: OBUFT port map (I => DATA_DWN_O(17) , T=> not_oe_ddwn, O => DATA_DWN(17) ) ; PO_DATADWN18: OBUFT port map (I => DATA_DWN_O(18) , T=> not_oe_ddwn, O => DATA_DWN(18) ) ; PO_DATADWN19: OBUFT port map (I => DATA_DWN_O(19) , T=> not_oe_ddwn, O => DATA_DWN(19) ) ; PO_DATADWN20: OBUFT port map (I => DATA_DWN_O(20) , T=> not_oe_ddwn, O => DATA_DWN(20) ) ; PO_DATADWN21: OBUFT port map (I => DATA_DWN_O(21) , T=> not_oe_ddwn, O => DATA_DWN(21) ) ; PO_DATADWN22: OBUFT port map (I => DATA_DWN_O(22) , T=> not_oe_ddwn, O => DATA_DWN(22) ) ; PO_DATADWN23: OBUFT port map (I => DATA_DWN_O(23) , T=> not_oe_ddwn, O => DATA_DWN(23) ) ; PO_DATADWN24: OBUFT port map (I => DATA_DWN_O(24) , T=> not_oe_ddwn, O => DATA_DWN(24) ) ; PO_DATADWN25: OBUFT port map (I => DATA_DWN_O(25) , T=> not_oe_ddwn, O => DATA_DWN(25) ) ; PO_DATADWN26: OBUFT port map (I => DATA_DWN_O(26) , T=> not_oe_ddwn, O => DATA_DWN(26) ) ; PO_DATADWN27: OBUFT port map (I => DATA_DWN_O(27) , T=> not_oe_ddwn, O => DATA_DWN(27) ) ; PO_DATADWN28: OBUFT port map (I => DATA_DWN_O(28) , T=> not_oe_ddwn, O => DATA_DWN(28) ) ; PO_DATADWN29: OBUFT port map (I => DATA_DWN_O(29) , T=> not_oe_ddwn, O => DATA_DWN(29) ) ; PO_DATADWN30: OBUFT port map (I => DATA_DWN_O(30) , T=> not_oe_ddwn, O => DATA_DWN(30) ) ; PO_DATADWN31: OBUFT port map (I => DATA_DWN_O(31) , T=> not_oe_ddwn, O => DATA_DWN(31) ) ; PO_DATADWN32: OBUFT port map (I => DATA_DWN_O(32) , T=> not_oe_ddwn, O => DATA_DWN(32) ) ; -- CONNECTOR(15:0) CAN BE BI-DIRECTIONAL PINS PI_CONN0: IBUF port map (I => CONNECTOR(0), O => CONNECTOR_I(0) ); PI_CONN1: IBUF port map (I => CONNECTOR(1), O => CONNECTOR_I(1) ); PI_CONN2: IBUF port map (I => CONNECTOR(2), O => CONNECTOR_I(2) ); PI_CONN3: IBUF port map (I => CONNECTOR(3), O => CONNECTOR_I(3) ); PI_CONN4: IBUF port map (I => CONNECTOR(4), O => CONNECTOR_I(4) ); PI_CONN5: IBUF port map (I => CONNECTOR(5), O => CONNECTOR_I(5) ); PI_CONN6: IBUF port map (I => CONNECTOR(6), O => CONNECTOR_I(6) ); PI_CONN7: IBUF port map (I => CONNECTOR(7), O => CONNECTOR_I(7) ); PI_CONN8: IBUF port map (I => CONNECTOR(8), O => CONNECTOR_I(8) ); PI_CONN9: IBUF port map (I => CONNECTOR(9), O => CONNECTOR_I(9) ); PI_CONN10: IBUF port map (I => CONNECTOR(10), O => CONNECTOR_I(10) ); PI_CONN11: IBUF port map (I => CONNECTOR(11), O => CONNECTOR_I(11) ); PI_CONN12: IBUF port map (I => CONNECTOR(12), O => CONNECTOR_I(12) ); PI_CONN13: IBUF port map (I => CONNECTOR(13), O => CONNECTOR_I(13) ); PI_CONN14: IBUF port map (I => CONNECTOR(14), O => CONNECTOR_I(14) ); PI_CONN15: IBUF port map (I => CONNECTOR(15), O => CONNECTOR_I(15) ); PO_CONN0: OBUFT port map (I => CONNECTOR_O(0) , T=> not_oe_conn, O => CONNECTOR(0) ) ; PO_CONN1: OBUFT port map (I => CONNECTOR_O(1) , T=> not_oe_conn, O => CONNECTOR(1) ) ; PO_CONN2: OBUFT port map (I => CONNECTOR_O(2) , T=> not_oe_conn, O => CONNECTOR(2) ) ; PO_CONN3: OBUFT port map (I => CONNECTOR_O(3) , T=> not_oe_conn, O => CONNECTOR(3) ) ; PO_CONN4: OBUFT port map (I => CONNECTOR_O(4) , T=> not_oe_conn, O => CONNECTOR(4) ) ; PO_CONN5: OBUFT port map (I => CONNECTOR_O(5) , T=> not_oe_conn, O => CONNECTOR(5) ) ; PO_CONN6: OBUFT port map (I => CONNECTOR_O(6) , T=> not_oe_conn, O => CONNECTOR(6) ) ; PO_CONN7: OBUFT port map (I => CONNECTOR_O(7) , T=> not_oe_conn, O => CONNECTOR(7) ) ; PO_CONN8: OBUFT port map (I => CONNECTOR_O(8) , T=> not_oe_conn, O => CONNECTOR(8) ) ; PO_CONN9: OBUFT port map (I => CONNECTOR_O(9) , T=> not_oe_conn, O => CONNECTOR(9) ) ; PO_CONN10: OBUFT port map (I => CONNECTOR_O(10) , T=> not_oe_conn, O => CONNECTOR(10) ) ; PO_CONN11: OBUFT port map (I => CONNECTOR_O(11) , T=> not_oe_conn, O => CONNECTOR(11) ) ; PO_CONN12: OBUFT port map (I => CONNECTOR_O(12) , T=> not_oe_conn, O => CONNECTOR(12) ) ; PO_CONN13: OBUFT port map (I => CONNECTOR_O(13) , T=> not_oe_conn, O => CONNECTOR(13) ) ; PO_CONN14: OBUFT port map (I => CONNECTOR_O(14) , T=> not_oe_conn, O => CONNECTOR(14) ) ; PO_CONN15: OBUFT port map (I => CONNECTOR_O(15) , T=> not_oe_conn, O => CONNECTOR(15) ) ; -- PO_CONN0: OBUF port map (I => CONNECTOR_O(0) , O => CONNECTOR(0) ); -- PO_CONN1: OBUF port map (I => CONNECTOR_O(1) , O => CONNECTOR(1) ); -- PO_CONN2: OBUF port map (I => CONNECTOR_O(2) , O => CONNECTOR(2) ); -- PO_CONN3: OBUF port map (I => CONNECTOR_O(3) , O => CONNECTOR(3) ); -- PO_CONN4: OBUF port map (I => CONNECTOR_O(4) , O => CONNECTOR(4) ); -- PO_CONN5: OBUF port map (I => CONNECTOR_O(5) , O => CONNECTOR(5) ); -- PO_CONN6: OBUF port map (I => CONNECTOR_O(6) , O => CONNECTOR(6) ); -- PO_CONN7: OBUF port map (I => CONNECTOR_O(7) , O => CONNECTOR(7) ); -- PO_CONN8: OBUF port map (I => CONNECTOR_O(8) , O => CONNECTOR(8) ); -- PO_CONN9: OBUF port map (I => CONNECTOR_O(9) , O => CONNECTOR(9) ); -- PO_CONN10: OBUF port map (I => CONNECTOR_O(10), O => CONNECTOR(10)); -- PO_CONN11: OBUF port map (I => CONNECTOR_O(11), O => CONNECTOR(11)); -- PO_CONN12: OBUF port map (I => CONNECTOR_O(12), O => CONNECTOR(12)); -- PO_CONN13: OBUF port map (I => CONNECTOR_O(13), O => CONNECTOR(13)); -- PO_CONN14: OBUF port map (I => CONNECTOR_O(14), O => CONNECTOR(14)); -- PO_CONN15: OBUF port map (I => CONNECTOR_O(15), O => CONNECTOR(15)); -- GENERICO(2:1) CAN BE BI-DIRECTIONAL PINS PI_GENERIC1: IBUF port map (I => GENERICO(1), O => GENERICO_I(1) ) ; PI_GENERIC2: IBUF port map (I => GENERICO(2), O => GENERICO_I(2) ) ; PO_GENERIC1: OBUFT port map (I => GENERICO_O(1) , T=> not_oe_gen, O => GENERICO(1) ) ; PO_GENERIC2: OBUFT port map (I => GENERICO_O(2) , T=> not_oe_gen, O => GENERICO(2) ) ; -- =================================================================== end buffers;