-- =======================================================================
-- Author:  Antonio Esteves, GEC-DI-UM.
-- File:    ffd_rst_sset.vhd
-- Date:    02 August 2000
--
-- D flip-flop with asynchronous reset and synchronous set.
-- =======================================================================

library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.std_logic_unsigned.all;

-- flip-flop with asynchronous reset and synchronous set

entity ffd_rst_syncset is   
    port (
       data_in    : in    std_logic;
       clock      : in    std_logic;
       reset      : in    std_logic;
       set        : in    std_logic;
       data_out   : out   std_logic
       );
end ffd_rst_syncset ;

architecture rtl of ffd_rst_syncset  is

   signal d_in : std_logic;

begin
   
    -- mux2:1 that implements the synchronous set of the flip-flop

    process (set, data_in)
    begin
       if (set = '1') then
          d_in <= '1' ;
       else
          d_in <= data_in ;
       end if;
    end process;

   -- flip-flop with asynchronous reset

   process (reset, clock)
   begin
      if (reset='1') then 
         data_out <= '0';
      elsif (clock'event and clock='1') then
         data_out <= d_in ;
      end if;
   end process;

end rtl;