-- ======================================================================= -- Author: Antonio Esteves, GEC-DI-UM. -- File: cnt_dwn_1vez.vhd -- Date: 13 August 2000 -- -- Loadable w-bit Down Counter, that stops when arriving to ZERO. -- Targeted to XC4xxx family. -- ======================================================================= library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY counterDown IS generic(w: NATURAL); PORT( -- counter start value:(w-1 downto 0) start : IN std_logic_vector(w-1 downto 0); c : IN std_logic; -- counter clock -- order to load start value into counter load : IN std_logic; reset : IN std_logic; -- counter reset -- counter output: (w-1 downto 0) count : INOUT std_logic_vector(w-1 downto 0); counting : INOUT std_logic -- indicates that 'count' is not ZERO ) ; END counterDown; ARCHITECTURE behav OF counterDown IS signal count_in : std_logic_vector(count'range) ; signal n_count : std_logic_vector(count'range) ; signal clk_en : std_logic; BEGIN clk_en <= counting or load; n_count <= count - 1; -- register input selector: start value or next count value process (load, start, n_count) begin if (load = '1') then count_in <= start; else count_in <= n_count; end if; end process; -- register with reset and clock enable process (c, clk_en, reset) begin if (reset = '1') then RST: for n in count'range loop count(n) <= '0'; end loop RST; elsif (c'event and c = '1') then if (clk_en = '1') then count <= count_in; end if; end if; end process; -- generation of the signal that stops the counter process (count) begin if (count /= 0) then counting <= '1' ; else counting <= '0' ; end if; end process; end behav;