-- -----------------------------------------------------------------------
 -- FILE:    registerD_ce_rst.vhd
 -- DATE:    17 November 2000
 -- AUTHOR:  Antonio Esteves, GEC-DI-UM
 --
 -- Register with D Flip-flops, clock enable and asynchronous reset.
 -- -----------------------------------------------------------------------

 library IEEE;
 use     IEEE.std_logic_1164.all;
 use     IEEE.std_logic_unsigned.all;

 ENTITY registerD_ce_rst IS

    generic (w: NATURAL);
    PORT (
        data_in     : in    std_logic_vector(w-1 downto 0);
        clock       : in    std_logic;
        enable      : in    std_logic;
         reset      : in    std_logic;
        data_out    : out   std_logic_vector(w-1 downto 0)
        ) ;
 END registerD_ce_rst;

 ARCHITECTURE rtl OF registerD_ce_rst IS
 BEGIN

    process (reset, clock, enable)
    begin
        if (reset='1') then
            RST: for n in data_out'range loop
                data_out(n) <= '0';
            end loop RST;
        elsif (clock'event and clock='1') then
            if (enable='1')  then
                data_out <= data_in ;
            end if;
        end if;
    end process;

 end rtl;

 -- -----------------------------------------------------------------------