-- ----------------------------------------------------------------------- -- FILE: interface_ctl.vhd -- DATE: 26 November 2000 -- AUTHOR: Antonio Esteves, GEC-DI-UM -- -- MODULE THAT GENERATES THE CONTROL SIGNALS USED TO READ (WRITE) FROM -- (TO) AN FPGA THROUGH THE PCI BUS. -- ----------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; -- +-------------------------+---------+---------+------------+------------+ -- | SIGNAL | A17 A16 | A15..A7 | A6 A5..A2 | ADDRESS | -- +-------------------------+---------+---------+------------+------------+ -- | notOEdoutB0 | 0 0 | x..x | x 0000 | 00 | -- | notOEdoutB1 | 0 0 | x..x | x 0001 | 04 | -- | notOEdoutB2 | 0 0 | x..x | x 0010 | 08 | -- | notOEdoutB3 | 0 0 | x..x | x 0011 | 0C | -- | notOEdoutB4 | 0 0 | x..x | x 0100 | 10 | -- | notOEdoutB5 | 0 0 | x..x | x 0101 | 14 | -- | notOEdoutB6 | 0 0 | x..x | x 0110 | 18 | -- | notOEdoutB7 | 0 0 | x..x | x 0111 | 1C | -- | | | | | | -- | notOEreadNewData | 0 0 | x..x | x 1000 | 20 | -- | notOEwriteData | 0 0 | x..x | x 1001 | 24 | -- +-------------------------+---------+---------+------------+------------+ -- | LOADdinB0 | 0 0 | x..x | 0 0000 | 00 | -- | LOADdinB1 | 0 0 | x..x | 0 0001 | 04 | -- | LOADdinB2 | 0 0 | x..x | 0 0010 | 08 | -- | LOADdinB3 | 0 0 | x..x | 0 0011 | 0C | -- | LOADdinB4 | 0 0 | x..x | 0 0100 | 10 | -- | LOADdinB5 | 0 0 | x..x | 0 0101 | 14 | -- | LOADdinB6 | 0 0 | x..x | 0 0110 | 18 | -- | LOADdinB7 | 0 0 | x..x | 0 0111 | 1C | -- | | | | | | -- | LOADkeyInB0 | 0 0 | x..x | 0 1000 | 20 | -- | LOADkeyInB1 | 0 0 | x..x | 0 1001 | 24 | -- | LOADkeyInB2 | 0 0 | x..x | 0 1010 | 28 | -- | LOADkeyInB3 | 0 0 | x..x | 0 1011 | 2C | -- | LOADkeyInB4 | 0 0 | x..x | 0 1100 | 30 | -- | LOADkeyInB5 | 0 0 | x..x | 0 1101 | 34 | -- | LOADkeyInB6 | 0 0 | x..x | 0 1110 | 38 | -- | LOADkeyInB7 | 0 0 | x..x | 0 1111 | 3C | -- | | | | | | -- | LOADdinValid | 0 0 | x..x | 1 0000 | 40 | -- | LOADencryptIn | 0 0 | x..x | 1 0001 | 44 | -- | LOADwriteDone | 0 0 | x..x | 1 0010 | 48 | -- | | | | | | -- | LOADresetFf | 0 0 | x..x | 1 0011 | 4C | -- | LOADstartFsm | 0 0 | x..x | 1 0100 | 50 | -- +-------------------------+---------+---------+------------+------------+ -- ------------------------------------------------------------------ -- FPGA INTERFACE CONTROLLER entity entity ctl_fpga_interface is port ( NOTWR_I : in std_logic ; NOTRD_I : in std_logic ; RESET_I : in std_logic ; PCLOCK_I : in std_logic ; BASE_HIT0_I : in std_logic ; ADDR_VLD_I : in std_logic ; S_DATA_VLD_I : in std_logic ; PCI_CMD7_I : in std_logic ; PCI_CMD6_I : in std_logic ; ADDR_I : in std_logic_vector(17 downto 0) ; S_DATA_I : in std_logic ; notOEdoutB0 : out STD_LOGIC; notOEdoutB1 : out STD_LOGIC; notOEdoutB2 : out STD_LOGIC; notOEdoutB3 : out STD_LOGIC; notOEdoutB4 : out STD_LOGIC; notOEdoutB5 : out STD_LOGIC; notOEdoutB6 : out STD_LOGIC; notOEdoutB7 : out STD_LOGIC; notOEreadNewData : out STD_LOGIC; notOEwriteData : out STD_LOGIC; LOADdinB0 : out STD_LOGIC; LOADdinB1 : out STD_LOGIC; LOADdinB2 : out STD_LOGIC; LOADdinB3 : out STD_LOGIC; LOADdinB4 : out STD_LOGIC; LOADdinB5 : out STD_LOGIC; LOADdinB6 : out STD_LOGIC; LOADdinB7 : out STD_LOGIC; LOADkeyInB0 : out STD_LOGIC; LOADkeyInB1 : out STD_LOGIC; LOADkeyInB2 : out STD_LOGIC; LOADkeyInB3 : out STD_LOGIC; LOADkeyInB4 : out STD_LOGIC; LOADkeyInB5 : out STD_LOGIC; LOADkeyInB6 : out STD_LOGIC; LOADkeyInB7 : out STD_LOGIC; LOADdinValid : out STD_LOGIC; LOADencryptIn : out STD_LOGIC; LOADwriteDone : out STD_LOGIC; LOADresetFf : out STD_LOGIC; LOADstartFsm : out STD_LOGIC ); end ctl_fpga_interface ; -- end of FPGA INTERFACE CONTROLLER entity -- -------------------------------------------------------------- architecture ffs_e_muxes of ctl_fpga_interface is signal delayed_reset, global_deassert, q_deassert : std_logic ; -- "readNewData" signal csRDreadNewData, rstRDreadNewData, setRDreadNewData, dRDreadNewData, notOErdreadNewData : std_logic; -- "writeData" signal csRDwriteData, rstRDwriteData, setRDwriteData, dRDwriteData, notOErdwriteData : std_logic; -- Byte 0 of "din" signal csWRdinB0, setWRdinB0, rstWrdinB0, LOADwrdinB0, d1WRdinB0, q1WRdinB0 : std_logic ; -- Byte 1 of "din" signal csWRdinB1, setWRdinB1, rstWrdinB1, LOADwrdinB1, d1WRdinB1, q1WRdinB1 : std_logic ; -- Byte 2 of "din" signal csWRdinB2, setWRdinB2, rstWrdinB2, LOADwrdinB2, d1WRdinB2, q1WRdinB2 : std_logic ; -- Byte 3 of "din" signal csWRdinB3, setWRdinB3, rstWrdinB3, LOADwrdinB3, d1WRdinB3, q1WRdinB3 : std_logic ; -- Byte 4 of "din" signal csWRdinB4, setWRdinB4, rstWrdinB4, LOADwrdinB4, d1WRdinB4, q1WRdinB4 : std_logic ; -- Byte 5 of "din" signal csWRdinB5, setWRdinB5, rstWrdinB5, LOADwrdinB5, d1WRdinB5, q1WRdinB5 : std_logic ; -- Byte 6 of "din" signal csWRdinB6, setWRdinB6, rstWrdinB6, LOADwrdinB6, d1WRdinB6, q1WRdinB6 : std_logic ; -- Byte 7 of "din" signal csWRdinB7, setWRdinB7, rstWrdinB7, LOADwrdinB7, d1WRdinB7, q1WRdinB7 : std_logic ; -- Byte 0 of "keyIn" signal csWRkeyInB0, setWRkeyInB0, rstWrkeyInB0, LOADwrkeyInB0, d1WRkeyInB0, q1WRkeyInB0 : std_logic ; -- Byte 1 of "keyIn" signal csWRkeyInB1, setWRkeyInB1, rstWrkeyInB1, LOADwrkeyInB1, d1WRkeyInB1, q1WRkeyInB1 : std_logic ; -- Byte 2 of "keyIn" signal csWRkeyInB2, setWRkeyInB2, rstWrkeyInB2, LOADwrkeyInB2, d1WRkeyInB2, q1WRkeyInB2 : std_logic ; -- Byte 3 of "keyIn" signal csWRkeyInB3, setWRkeyInB3, rstWrkeyInB3, LOADwrkeyInB3, d1WRkeyInB3, q1WRkeyInB3 : std_logic ; -- Byte 4 of "keyIn" signal csWRkeyInB4, setWRkeyInB4, rstWrkeyInB4, LOADwrkeyInB4, d1WRkeyInB4, q1WRkeyInB4 : std_logic ; -- Byte 5 of "keyIn" signal csWRkeyInB5, setWRkeyInB5, rstWrkeyInB5, LOADwrkeyInB5, d1WRkeyInB5, q1WRkeyInB5 : std_logic ; -- Byte 6 of "keyIn" signal csWRkeyInB6, setWRkeyInB6, rstWrkeyInB6, LOADwrkeyInB6, d1WRkeyInB6, q1WRkeyInB6 : std_logic ; -- Byte 7 of "keyIn" signal csWRkeyInB7, setWRkeyInB7, rstWrkeyInB7, LOADwrkeyInB7, d1WRkeyInB7, q1WRkeyInB7 : std_logic ; -- "dinValid" signal csWRdinValid, setWRdinValid, rstWrdinValid, LOADwrdinValid, d1WRdinValid, q1WRdinValid : std_logic ; -- "encryptIn" signal csWRencryptIn, setWRencryptIn, rstWrencryptIn, LOADwrencryptIn, d1WRencryptIn, q1WRencryptIn : std_logic ; -- "writeDone" signal csWRwriteDone, setWRwriteDone, rstWrwriteDone, LOADwrwriteDone, d1WRwriteDone, q1WRwriteDone : std_logic ; -- "resetFf" signal csWRresetFf, setWRresetFf, rstWrresetFf, LOADwrresetFf, d1WRresetFf, q1WRresetFf : std_logic ; -- "startFsm" signal csWRstartFsm, setWRstartFsm, rstWrstartFsm, LOADwrstartFsm, d1WRstartFsm, q1WRstartFsm : std_logic ; begin notOEreadNewData <= notOErdreadNewData; notOEwriteData <= notOErdwriteData; LOADdinB0 <= LOADwrdinB0; LOADdinB1 <= LOADwrdinB1; LOADdinB2 <= LOADwrdinB2; LOADdinB3 <= LOADwrdinB3; LOADdinB4 <= LOADwrdinB4; LOADdinB5 <= LOADwrdinB5; LOADdinB6 <= LOADwrdinB6; LOADdinB7 <= LOADwrdinB7; LOADkeyInB0 <= LOADwrkeyInB0; LOADkeyInB1 <= LOADwrkeyInB1; LOADkeyInB2 <= LOADwrkeyInB2; LOADkeyInB3 <= LOADwrkeyInB3; LOADkeyInB4 <= LOADwrkeyInB4; LOADkeyInB5 <= LOADwrkeyInB5; LOADkeyInB6 <= LOADwrkeyInB6; LOADkeyInB7 <= LOADwrkeyInB7; LOADdinValid <= LOADwrdinValid; LOADencryptIn <= LOADwrencryptIn; LOADwriteDone <= LOADwrwriteDone; LOADresetFf <= LOADwrresetFf; LOADstartFsm <= LOADwrstartFsm; -- ------------------------------------------------------------- delayed_reset <= RESET_I ; -- ------------------------------------------------------------- -- Generation of a global signal that will be used to -- -- deassert (put high) all the output enable's (active low) -- -- ------------------------------------------------------------- -- flip-flop process (S_DATA_I, ADDR_VLD_I, delayed_reset) begin if ( (ADDR_VLD_I='1') or (delayed_reset='1') ) then -- reset q_deassert <= '0' ; elsif (S_DATA_I'event and S_DATA_I='0') then -- falling edge clock q_deassert <= '1' ; end if; end process; global_deassert <= delayed_reset or q_deassert or (ADDR_VLD_I and (not PCLOCK_I)) ; -- ----------------------------------------------------------------- -- "output enable" to read "readNewData" (/OE) -- -- ADDR[17:0] = 00 xxxx xxxx xx10 00xx = (00020 hex) -- -- ----------------------------------------------------------------- csRDreadNewData <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(5) and (not ADDR_I(4)) and (not ADDR_I(3)) and (not ADDR_I(2)); rstRDreadNewData <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and csRDreadNewData and (not PCLOCK_I) ) ; setRDreadNewData <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (setRDreadNewData, notOErdreadNewData) begin if (setRDreadNewData='0') then dRDreadNewData <= notOErdreadNewData ; else dRDreadNewData <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rstRDreadNewData, PCLOCK_I) begin if (rstRDreadNewData='1') then notOErdreadNewData <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then notOErdreadNewData <= dRDreadNewData ; end if; end process; -- ----------------------------------------------------------------- -- "output enable" to read "writeData" (/OE) -- -- ADDR[17:0] = 00 xxxx xxxx xx10 01xx = (00024 hex) -- -- ----------------------------------------------------------------- csRDwriteData <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(5) and (not ADDR_I(4)) and (not ADDR_I(3)) and ADDR_I(2); rstRDwriteData <= (BASE_HIT0_I and (not NOTRD_I) and PCI_CMD6_I and csRDwriteData and (not PCLOCK_I) ) ; setRDwriteData <= global_deassert ; -- mux2:1 that implements the synchronous set of a flip-flop process (setRDwriteData, notOErdwriteData) begin if (setRDwriteData='0') then dRDwriteData <= notOErdwriteData ; else dRDwriteData <= '1' ; end if; end process; -- flip-flop with asynchronous reset process (rstRDwriteData, PCLOCK_I) begin if (rstRDwriteData='1') then notOErdwriteData <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then notOErdwriteData <= dRDwriteData ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 0 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x000 00xx = (00000 hex ) -- -- ----------------------------------------------------------------- csWRdinB0 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and (not ADDR_I(4)) and (not ADDR_I(3)) and (not ADDR_I(2)); setWRdinB0 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB0 and (not PCLOCK_I) ; rstWrdinB0 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB0 <= q1WRdinB0 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB0, q1WRdinB0) begin if (setWRdinB0='1') then d1WRdinB0 <= '1'; else d1WRdinB0 <= q1WRdinB0 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB0, PCLOCK_I) begin if (rstWrdinB0='1') then -- reset q1WRdinB0 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB0 <= d1WRdinB0 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 1 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x000 01xx = (00004 hex ) -- -- ----------------------------------------------------------------- csWRdinB1 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and (not ADDR_I(4)) and (not ADDR_I(3)) and ADDR_I(2); setWRdinB1 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB1 and (not PCLOCK_I) ; rstWrdinB1 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB1 <= q1WRdinB1 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB1, q1WRdinB1) begin if (setWRdinB1='1') then d1WRdinB1 <= '1'; else d1WRdinB1 <= q1WRdinB1 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB1, PCLOCK_I) begin if (rstWrdinB1='1') then -- reset q1WRdinB1 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB1 <= d1WRdinB1 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 2 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x000 10xx = (00008 hex ) -- -- ----------------------------------------------------------------- csWRdinB2 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and (not ADDR_I(4)) and ADDR_I(3) and (not ADDR_I(2)); setWRdinB2 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB2 and (not PCLOCK_I) ; rstWrdinB2 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB2 <= q1WRdinB2 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB2, q1WRdinB2) begin if (setWRdinB2='1') then d1WRdinB2 <= '1'; else d1WRdinB2 <= q1WRdinB2 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB2, PCLOCK_I) begin if (rstWrdinB2='1') then -- reset q1WRdinB2 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB2 <= d1WRdinB2 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 3 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x000 11xx = (0000C hex ) -- -- ----------------------------------------------------------------- csWRdinB3 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and (not ADDR_I(4)) and ADDR_I(3) and ADDR_I(2); setWRdinB3 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB3 and (not PCLOCK_I) ; rstWrdinB3 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB3 <= q1WRdinB3 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB3, q1WRdinB3) begin if (setWRdinB3='1') then d1WRdinB3 <= '1'; else d1WRdinB3 <= q1WRdinB3 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB3, PCLOCK_I) begin if (rstWrdinB3='1') then -- reset q1WRdinB3 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB3 <= d1WRdinB3 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 4 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x001 00xx = (00010 hex ) -- -- ----------------------------------------------------------------- csWRdinB4 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and ADDR_I(4) and (not ADDR_I(3)) and (not ADDR_I(2)); setWRdinB4 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB4 and (not PCLOCK_I) ; rstWrdinB4 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB4 <= q1WRdinB4 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB4, q1WRdinB4) begin if (setWRdinB4='1') then d1WRdinB4 <= '1'; else d1WRdinB4 <= q1WRdinB4 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB4, PCLOCK_I) begin if (rstWrdinB4='1') then -- reset q1WRdinB4 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB4 <= d1WRdinB4 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 5 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x001 01xx = (00014 hex ) -- -- ----------------------------------------------------------------- csWRdinB5 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and ADDR_I(4) and (not ADDR_I(3)) and ADDR_I(2); setWRdinB5 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB5 and (not PCLOCK_I) ; rstWrdinB5 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB5 <= q1WRdinB5 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB5, q1WRdinB5) begin if (setWRdinB5='1') then d1WRdinB5 <= '1'; else d1WRdinB5 <= q1WRdinB5 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB5, PCLOCK_I) begin if (rstWrdinB5='1') then -- reset q1WRdinB5 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB5 <= d1WRdinB5 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 6 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x001 10xx = (00018 hex ) -- -- ----------------------------------------------------------------- csWRdinB6 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and ADDR_I(4) and ADDR_I(3) and (not ADDR_I(2)); setWRdinB6 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB6 and (not PCLOCK_I) ; rstWrdinB6 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB6 <= q1WRdinB6 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB6, q1WRdinB6) begin if (setWRdinB6='1') then d1WRdinB6 <= '1'; else d1WRdinB6 <= q1WRdinB6 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB6, PCLOCK_I) begin if (rstWrdinB6='1') then -- reset q1WRdinB6 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB6 <= d1WRdinB6 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 7 of "din" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x001 11xx = (0001C hex ) -- -- ----------------------------------------------------------------- csWRdinB7 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and (not ADDR_I(5)) and ADDR_I(4) and ADDR_I(3) and ADDR_I(2); setWRdinB7 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinB7 and (not PCLOCK_I) ; rstWrdinB7 <= ADDR_VLD_I or delayed_reset ; LOADwrdinB7 <= q1WRdinB7 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinB7, q1WRdinB7) begin if (setWRdinB7='1') then d1WRdinB7 <= '1'; else d1WRdinB7 <= q1WRdinB7 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinB7, PCLOCK_I) begin if (rstWrdinB7='1') then -- reset q1WRdinB7 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinB7 <= d1WRdinB7 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 0 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x010 00xx = (00020 hex ) -- -- ----------------------------------------------------------------- csWRkeyInB0 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and (not ADDR_I(4)) and (not ADDR_I(3)) and (not ADDR_I(2)); setWRkeyInB0 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB0 and (not PCLOCK_I) ; rstWrkeyInB0 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB0 <= q1WRkeyInB0 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB0, q1WRkeyInB0) begin if (setWRkeyInB0='1') then d1WRkeyInB0 <= '1'; else d1WRkeyInB0 <= q1WRkeyInB0 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB0, PCLOCK_I) begin if (rstWrkeyInB0='1') then -- reset q1WRkeyInB0 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB0 <= d1WRkeyInB0 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 1 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x010 01xx = (00024 hex ) -- -- ----------------------------------------------------------------- csWRkeyInB1 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and (not ADDR_I(4)) and (not ADDR_I(3)) and ADDR_I(2); setWRkeyInB1 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB1 and (not PCLOCK_I) ; rstWrkeyInB1 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB1 <= q1WRkeyInB1 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB1, q1WRkeyInB1) begin if (setWRkeyInB1='1') then d1WRkeyInB1 <= '1'; else d1WRkeyInB1 <= q1WRkeyInB1 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB1, PCLOCK_I) begin if (rstWrkeyInB1='1') then -- reset q1WRkeyInB1 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB1 <= d1WRkeyInB1 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 2 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x010 10xx = (00028 hex ) -- -- ----------------------------------------------------------------- csWRkeyInB2 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and (not ADDR_I(4)) and ADDR_I(3) and (not ADDR_I(2)); setWRkeyInB2 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB2 and (not PCLOCK_I) ; rstWrkeyInB2 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB2 <= q1WRkeyInB2 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB2, q1WRkeyInB2) begin if (setWRkeyInB2='1') then d1WRkeyInB2 <= '1'; else d1WRkeyInB2 <= q1WRkeyInB2 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB2, PCLOCK_I) begin if (rstWrkeyInB2='1') then -- reset q1WRkeyInB2 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB2 <= d1WRkeyInB2 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 3 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x010 11xx = (0002C hex ) -- -- ----------------------------------------------------------------- csWRkeyInB3 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and (not ADDR_I(4)) and ADDR_I(3) and ADDR_I(2); setWRkeyInB3 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB3 and (not PCLOCK_I) ; rstWrkeyInB3 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB3 <= q1WRkeyInB3 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB3, q1WRkeyInB3) begin if (setWRkeyInB3='1') then d1WRkeyInB3 <= '1'; else d1WRkeyInB3 <= q1WRkeyInB3 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB3, PCLOCK_I) begin if (rstWrkeyInB3='1') then -- reset q1WRkeyInB3 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB3 <= d1WRkeyInB3 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 4 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x011 00xx = (00030 hex ) -- -- ----------------------------------------------------------------- csWRkeyInB4 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and ADDR_I(4) and (not ADDR_I(3)) and (not ADDR_I(2)); setWRkeyInB4 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB4 and (not PCLOCK_I) ; rstWrkeyInB4 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB4 <= q1WRkeyInB4 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB4, q1WRkeyInB4) begin if (setWRkeyInB4='1') then d1WRkeyInB4 <= '1'; else d1WRkeyInB4 <= q1WRkeyInB4 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB4, PCLOCK_I) begin if (rstWrkeyInB4='1') then -- reset q1WRkeyInB4 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB4 <= d1WRkeyInB4 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 5 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x011 01xx = (00034 hex ) -- -- ----------------------------------------------------------------- csWRkeyInB5 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and ADDR_I(4) and (not ADDR_I(3)) and ADDR_I(2); setWRkeyInB5 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB5 and (not PCLOCK_I) ; rstWrkeyInB5 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB5 <= q1WRkeyInB5 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB5, q1WRkeyInB5) begin if (setWRkeyInB5='1') then d1WRkeyInB5 <= '1'; else d1WRkeyInB5 <= q1WRkeyInB5 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB5, PCLOCK_I) begin if (rstWrkeyInB5='1') then -- reset q1WRkeyInB5 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB5 <= d1WRkeyInB5 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 6 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x011 10xx = (00038 hex ) -- -- ----------------------------------------------------------------- csWRkeyInB6 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and ADDR_I(4) and ADDR_I(3) and (not ADDR_I(2)); setWRkeyInB6 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB6 and (not PCLOCK_I) ; rstWrkeyInB6 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB6 <= q1WRkeyInB6 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB6, q1WRkeyInB6) begin if (setWRkeyInB6='1') then d1WRkeyInB6 <= '1'; else d1WRkeyInB6 <= q1WRkeyInB6 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB6, PCLOCK_I) begin if (rstWrkeyInB6='1') then -- reset q1WRkeyInB6 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB6 <= d1WRkeyInB6 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to byte 7 of "keyIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x011 11xx = (0003C hex ) -- -- ----------------------------------------------------------------- csWRkeyInB7 <= (not ADDR_I(17)) and (not ADDR_I(16)) and (not ADDR_I(6)) and ADDR_I(5) and ADDR_I(4) and ADDR_I(3) and ADDR_I(2); setWRkeyInB7 <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRkeyInB7 and (not PCLOCK_I) ; rstWrkeyInB7 <= ADDR_VLD_I or delayed_reset ; LOADwrkeyInB7 <= q1WRkeyInB7 and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRkeyInB7, q1WRkeyInB7) begin if (setWRkeyInB7='1') then d1WRkeyInB7 <= '1'; else d1WRkeyInB7 <= q1WRkeyInB7 ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrkeyInB7, PCLOCK_I) begin if (rstWrkeyInB7='1') then -- reset q1WRkeyInB7 <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRkeyInB7 <= d1WRkeyInB7 ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to "dinValid" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x100 00xx = (00040 hex ) -- -- ----------------------------------------------------------------- csWRdinValid <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(6) and (not ADDR_I(5)) and (not ADDR_I(4)) and (not ADDR_I(3)) and (not ADDR_I(2)); setWRdinValid <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRdinValid and (not PCLOCK_I) ; rstWrdinValid <= ADDR_VLD_I or delayed_reset ; LOADwrdinValid <= q1WRdinValid and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRdinValid, q1WRdinValid) begin if (setWRdinValid='1') then d1WRdinValid <= '1'; else d1WRdinValid <= q1WRdinValid ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrdinValid, PCLOCK_I) begin if (rstWrdinValid='1') then -- reset q1WRdinValid <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRdinValid <= d1WRdinValid ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to "encryptIn" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x100 01xx = (00044 hex ) -- -- ----------------------------------------------------------------- csWRencryptIn <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(6) and (not ADDR_I(5)) and (not ADDR_I(4)) and (not ADDR_I(3)) and ADDR_I(2); setWRencryptIn <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRencryptIn and (not PCLOCK_I) ; rstWrencryptIn <= ADDR_VLD_I or delayed_reset ; LOADwrencryptIn <= q1WRencryptIn and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRencryptIn, q1WRencryptIn) begin if (setWRencryptIn='1') then d1WRencryptIn <= '1'; else d1WRencryptIn <= q1WRencryptIn ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrencryptIn, PCLOCK_I) begin if (rstWrencryptIn='1') then -- reset q1WRencryptIn <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRencryptIn <= d1WRencryptIn ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to "writeDone" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x100 10xx = (00048 hex ) -- -- ----------------------------------------------------------------- csWRwriteDone <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(6) and (not ADDR_I(5)) and (not ADDR_I(4)) and ADDR_I(3) and (not ADDR_I(2)); setWRwriteDone <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRwriteDone and (not PCLOCK_I) ; rstWrwriteDone <= ADDR_VLD_I or delayed_reset ; LOADwrwriteDone <= q1WRwriteDone and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRwriteDone, q1WRwriteDone) begin if (setWRwriteDone='1') then d1WRwriteDone <= '1'; else d1WRwriteDone <= q1WRwriteDone ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrwriteDone, PCLOCK_I) begin if (rstWrwriteDone='1') then -- reset q1WRwriteDone <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRwriteDone <= d1WRwriteDone ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to "resetFf" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x100 11xx = (0004C hex ) -- -- ----------------------------------------------------------------- csWRresetFf <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(6) and (not ADDR_I(5)) and (not ADDR_I(4)) and ADDR_I(3) and ADDR_I(2); setWRresetFf <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRresetFf and (not PCLOCK_I) ; rstWrresetFf <= ADDR_VLD_I or delayed_reset ; LOADwrresetFf <= q1WRresetFf and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRresetFf, q1WRresetFf) begin if (setWRresetFf='1') then d1WRresetFf <= '1'; else d1WRresetFf <= q1WRresetFf ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrresetFf, PCLOCK_I) begin if (rstWrresetFf='1') then -- reset q1WRresetFf <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRresetFf <= d1WRresetFf ; end if; end process; -- ----------------------------------------------------------------- -- "write enable" to write to "startFsm" (LOAD) -- -- ADDR[17:0] = 00 xxxx xxxx x101 00xx = (00050 hex ) -- -- ----------------------------------------------------------------- csWRstartFsm <= (not ADDR_I(17)) and (not ADDR_I(16)) and ADDR_I(6) and (not ADDR_I(5)) and ADDR_I(4) and (not ADDR_I(3)) and (not ADDR_I(2)); setWRstartFsm <= BASE_HIT0_I and (not NOTWR_I) and PCI_CMD7_I and csWRstartFsm and (not PCLOCK_I) ; rstWrstartFsm <= ADDR_VLD_I or delayed_reset ; LOADwrstartFsm <= q1WRstartFsm and S_DATA_VLD_I ; -- mux2:1 that implements the synchronous set of a flip-flop process (setWRstartFsm, q1WRstartFsm) begin if (setWRstartFsm='1') then d1WRstartFsm <= '1'; else d1WRstartFsm <= q1WRstartFsm ; end if; end process; -- flip-flop D with asynchronous reset process (rstWrstartFsm, PCLOCK_I) begin if (rstWrstartFsm='1') then -- reset q1WRstartFsm <= '0' ; elsif (PCLOCK_I'event and PCLOCK_I='1') then -- clock rising edge q1WRstartFsm <= d1WRstartFsm ; end if; end process; end ffs_e_muxes; -- -----------------------------------------------------------------------