-- ----------------------------------------------------------------------- -- FILE: fsm0.vhd -- DATE: 2 December 2000 -- AUTHOR: Antonio Esteves, GEC-DI-UM -- -- FSM THAT CONTROLS THE EXECUTION OF THE PART ALLOCATED TO FPGA 0 -- (STAGE 0 or HW1 PARTITION) ON THE HW/SW IMPLEMENTATION OF DES. -- ----------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity fsm0 is port ( clk : in STD_LOGIC; resetFf : in STD_LOGIC; startFsm : in STD_LOGIC; newData : in STD_LOGIC; selectIn : in STD_LOGIC; selectOut : in STD_LOGIC; stage : in STD_LOGIC_VECTOR (1 downto 0); round : in STD_LOGIC_VECTOR (3 downto 0); -- NOT USED writeDone : in STD_LOGIC; dinValidMux : in STD_LOGIC; countingReads : in STD_LOGIC; doutValidR : in STD_LOGIC; notFirstTime : in std_logic; CEipPc1 : out STD_LOGIC; CEmuxedIn : out STD_LOGIC; CEdesEp : out STD_LOGIC; CEdesSbox : out STD_LOGIC; CEoutputsR : out STD_LOGIC; CEround : out STD_LOGIC; CEoutputs : out STD_LOGIC; CEwriteData : out STD_LOGIC; CEreadNewData : out STD_LOGIC; CEreadPrevStage : out STD_LOGIC; CEoutputValid : out STD_LOGIC; RSTreadNewData : out STD_LOGIC; RSTreadPrevStage : out STD_LOGIC; RSTwriteDone : out STD_LOGIC; RSTwriteData : out STD_LOGIC; RSTdinValids : out STD_LOGIC; RSTprevOutValids : out STD_LOGIC; RSTnewData : out STD_LOGIC; notRDprevStage : out STD_LOGIC; LOADcntReads : out STD_LOGIC; CLKcntReads : out STD_LOGIC; LOADenable : out STD_LOGIC; LOADdinValidR : out sTD_LOGIC ); end; architecture fsmArch0 of fsm0 is -- symbolic encoded state machine: fsmState type fsmStateType is ( read5dinValidR , read4dinValidR , read3dinValidR , read2dinValidR , read1dinValidR , wrOutputsR , desFpParitykey , waitOutRead , enableWriteData , waitWriteDone , desIpPc1Nshifts , enableRnewData , enableRprevStage , muxesA , muxesB , keyShiftsPc2 , desEp , desSboxA , desSboxB , desPbox , loadCntReads1 , loadCntReads2 , incCntReads , tstCntReads , read1others , read2others , read3others , read4others , read5others , wr1DoutValidR , wr2DoutValidR , wait1 , restart ); signal fsmState : fsmStateType; begin finite_state_machine: process (clk, resetFf) begin if resetFf='1' then fsmState <= read5dinValidR; elsif clk'event and clk='1' then case fsmState is when enableRnewData => CEreadNewData <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= loadCntReads1; when enableRprevStage => CEreadPrevStage <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= loadCntReads1; when loadCntReads1 => LOADcntReads <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= loadCntReads2; when loadCntReads2 => LOADcntReads <= '1'; CLKcntReads <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= read1dinValidR; when read1dinValidR => CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= read2dinValidR; when read2dinValidR => CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= read3dinValidR; when read3dinValidR => CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= read4dinValidR; when read4dinValidR => LOADdinValidR <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; fsmState <= read5dinValidR; when read5dinValidR => LOADdinValidR <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; if (startFsm='1') then fsmState <= restart; elsif (startFsm='0') and (dinValidMux='0') then fsmState <= read5dinValidR; elsif (startFsm='0') and (dinValidMux='1') then fsmState <= incCntReads; end if; when restart => RSTprevOutValids <= '1'; RSTnewData <= '1'; RSTdinValids <= '1'; RSTreadNewData <= '1'; RSTreadPrevStage <= '1'; RSTwriteDone <= '1'; RSTwriteData <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= enableRnewData; when incCntReads => CLKcntReads <= '1'; RSTreadNewData <= '1'; RSTreadPrevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= tstCntReads; when tstCntReads => CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; if (countingReads='0') then fsmState <= desIpPc1Nshifts; elsif (countingReads='1') then fsmState <= read1others; end if; when read1others => CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= read2others; when read2others => CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= read3others; when read3others => LOADenable <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADdinValidR <= '0'; fsmState <= read4others; when read4others => LOADenable <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADdinValidR <= '0'; fsmState <= read5others; when read5others => CLKcntReads <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; notRDprevStage <= '0'; LOADcntReads <= '0'; LOADdinValidR <= '0'; LOADenable <= '0'; fsmState <= tstCntReads; when desIpPc1Nshifts => notRDprevStage <= '1'; RSTprevOutValids <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; if (newData='1') then fsmState <= muxesA; elsif (newData='0') then fsmState <= muxesB; end if; when muxesA => CEipPc1 <= '1'; notRDprevStage <= '1'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= keyShiftsPc2; when muxesB => notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= keyShiftsPc2; when keyShiftsPc2 => CEmuxedIn <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= desEp; when desEp => RSTnewData <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= desSboxA; when desSboxA => CEdesEp <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= desSboxB; when desSboxB => notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= desPbox; when desPbox => CEdesSbox <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= waitOutRead; when waitOutRead => notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTprevOutValids <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; if (doutValidR='1') then fsmState <= waitOutRead; elsif (doutValidR='0') then fsmState <= wrOutputsR; end if; when wrOutputsR => CEoutputsR <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; if (selectOut='0') or (stage(1)='0') or (stage(0)='0') then fsmState <= wr1DoutValidR; elsif (selectOut='1') and (stage(1)='1') and (stage(0)='1') then fsmState <= desFpParitykey; end if; when desFpParitykey => notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= enableWriteData; when enableWriteData => CEoutputs <= '1'; CEwriteData <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= waitWriteDone; when waitWriteDone => notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; if (writeDone='1') then fsmState <= wr1DoutValidR; elsif (writeDone='0') then fsmState <= waitWriteDone; end if; when wr1DoutValidR => CEround <= '1'; CEoutputValid <= '1'; RSTwriteDone <= '1'; RSTwriteData <= '1'; RSTdinValids <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= wr2DoutValidR; when wr2DoutValidR => CEoutputValid <= '1'; notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEround <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; fsmState <= wait1; when wait1 => notRDprevStage <= '1'; CEipPc1 <= '0'; CEmuxedIn <= '0'; CEdesEp <= '0'; CEdesSbox <= '0'; CEoutputsR <= '0'; CEround <= '0'; CEoutputs <= '0'; CEwriteData <= '0'; CEreadNewData <= '0'; CEreadPrevStage <= '0'; CEoutputValid <= '0'; RSTreadNewData <= '0'; RSTreadPrevStage <= '0'; RSTwriteDone <= '0'; RSTwriteData <= '0'; RSTdinValids <= '0'; RSTprevOutValids <= '0'; RSTnewData <= '0'; CLKcntReads <= '0'; LOADcntReads <= '0'; LOADenable <= '0'; LOADdinValidR <= '0'; if (selectIn='0') and (stage(1)='0') and (stage(0)='0') then fsmState <= enableRnewData; elsif (selectIn='1') or ((selectIn='0') and ((stage(1)='1') or (stage(0)='1'))) then fsmState <= enableRprevStage; end if; when others => null; end case; end if; end process; end fsmArch0; -- -----------------------------------------------------------------------