-- -----------------------------------------------------------------------
 -- FILE:    ffd_ce.vhd
 -- DATE:    13 August 1999
 -- AUTHOR:  Antonio Esteves, GEC-DI-UM
 --
 -- D Flip-flop with clock enable.
 -- -----------------------------------------------------------------------

 library IEEE;
 use     IEEE.std_logic_1164.all;
 use     IEEE.std_logic_unsigned.all;

 -- flip-flop with clock enable

 entity ffd_ce is
    port (
        data_in     : in    std_logic;
        clock       : in    std_logic;
        enable      : in    std_logic;
        data_out    : out   std_logic
        );
 end ffd_ce ;

 architecture rtl of ffd_ce  is
 begin

    process (clock, enable)
    begin
        if (clock'event and clock='1') then
            if (enable='1')  then
                data_out <= data_in ;
            end if;
        end if;
    end process;

 end rtl;

 -- -----------------------------------------------------------------------