//////////////////////////////////////////////////////////////////////
// File: edgar2_lib.h
//
// Library for accessing the EDgAR-2 card.
// The code was generated by WinDriver Wizard.
// It accesses the hardware via WinDriver functions.
//
//////////////////////////////////////////////////////////////////////

#ifndef _EDGAR2_LIB_H_
#define _EDGAR2_LIB_H_

#include "windrvr.h"
#include "pci_regs.h"
#include "bits.h"

#ifdef __cplusplus
extern "C" {
#endif

enum { EDGAR2A_DEFAULT_VENDOR_ID = 0x10ee };
enum { EDGAR2A_DEFAULT_DEVICE_ID = 0x4013 };

typedef enum
    {
    EDGAR2A_MODE_BYTE   = 0,
    EDGAR2A_MODE_WORD   = 1,
    EDGAR2A_MODE_DWORD  = 2
    } EDGAR2A_MODE;

typedef enum
    {
    EDGAR2A_AD_BAR0  = 0,
    EDGAR2A_AD_BAR1  = 1,
    EDGAR2A_AD_BAR2  = 2,
    EDGAR2A_AD_BAR3  = 3,
    EDGAR2A_AD_BAR4  = 4,
    EDGAR2A_AD_BAR5  = 5,
    EDGAR2A_AD_EPROM = 6,
    EDGAR2A_ITEMS    = 7
    } EDGAR2A_ADDR;

// EDgAR-2 register definitions

enum { EDGAR2A_DONE_SPACE                   = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_DONE_OFFSET                  = 0x3d000 };
enum { EDGAR2A_notProgramFpga_SPACE         = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_notProgramFpga_OFFSET        = 0x3f000 };
enum { EDGAR2A_notINIT_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_notINIT_OFFSET               = 0x3e000 };
enum { EDGAR2A_fpgaRdyNotBusy_SPACE         = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_fpgaRdyNotBusy_OFFSET        = 0x28000 };
enum { EDGAR2A_interruptRequest_SPACE       = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_interruptRequest_OFFSET      = 0x39000 };
enum { EDGAR2A_cfg_1_SPACE                  = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_1_OFFSET                 = 0x22000 };
enum { EDGAR2A_cfg_0_SPACE                  = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_0_OFFSET                 = 0x21000 };
enum { EDGAR2A_cfg_2_SPACE                  = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_2_OFFSET                 = 0x24000 };
enum { EDGAR2A_cfg_3_SPACE                  = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_OFFSET                 = 0x28000 };
enum { EDGAR2A_cfg_1_0_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_1_0_OFFSET               = 0x23000 };
enum { EDGAR2A_cfg_2_0_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_2_0_OFFSET               = 0x25000 };
enum { EDGAR2A_cfg_3_0_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_0_OFFSET               = 0x29000 };
enum { EDGAR2A_cfg_3_1_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_1_OFFSET               = 0x2a000 };
enum { EDGAR2A_cfg_3_2_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_2_OFFSET               = 0x2c000 };
enum { EDGAR2A_cfg_2_1_0_SPACE              = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_2_1_0_OFFSET             = 0x27000 };
enum { EDGAR2A_cfg_3_2_0_SPACE              = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_2_0_OFFSET             = 0x2d000 };
enum { EDGAR2A_cfg_3_2_1_SPACE              = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_2_1_OFFSET             = 0x2e000 };
enum { EDGAR2A_cfg_3_2_1_0_SPACE            = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_2_1_0_OFFSET           = 0x2f000 };
enum { EDGAR2A_cfg_3_1_0_SPACE              = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_3_1_0_OFFSET             = 0x2b000 };
enum { EDGAR2A_cfg_2_1_SPACE                = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_cfg_2_1_OFFSET               = 0x26000 };
enum { EDGAR2A_enablePciCtlSignals_SPACE    = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_enablePciCtlSignals_OFFSET   = 0x3b000 };
enum { EDGAR2A_programJtagChain_SPACE       = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_programJtagChain_OFFSET      = 0x3a000 };
enum { EDGAR2A_SCLOCK_SPACE                 = EDGAR2A_AD_BAR0 };
enum { EDGAR2A_SCLOCK_OFFSET                = 0x3c000 };

typedef struct EDGAR2A_STRUCT *EDGAR2A_HANDLE;

typedef struct
    {
    DWORD dwCounter;   // number of interrupts received
    DWORD dwLost;      // number of interrupts not yet dealt with
    BOOL fStopped;     // was interrupt disabled during wait
    } EDGAR2A_INT_RESULT;

typedef void (WINAPI *EDGAR2A_INT_HANDLER)
    ( EDGAR2A_HANDLE hEDGAR2A, EDGAR2A_INT_RESULT *intResult);

typedef struct
    {
    WD_INTERRUPT Int;
    HANDLE hThread;
    WD_TRANSFER Trans[1];
    EDGAR2A_INT_HANDLER funcIntHandler;
    } EDGAR2A_INT_INTERRUPT;

typedef struct
    {
    DWORD index;
    DWORD dwMask;
    BOOL  fIsMemory;
    BOOL  fActive;
    } EDGAR2A_ADDR_DESC;

typedef struct EDGAR2A_STRUCT
    {
    HANDLE hWD;
    BOOL   fUseInt;
    EDGAR2A_INT_INTERRUPT Int;
    WD_PCI_SLOT pciSlot;
    EDGAR2A_ADDR_DESC addrDesc[EDGAR2A_ITEMS];
    WD_CARD_REGISTER cardReg;
    } EDGAR2A_STRUCT;

// Options for EDgAR-2_Open

enum { EDGAR2A_OPEN_USE_INT =   0x1 };

BOOL EDGAR2A_Open (EDGAR2A_HANDLE *phEDGAR2A, DWORD dwVendorID,
    DWORD dwDeviceID, DWORD nCardNum, DWORD options);
void EDGAR2A_Close(EDGAR2A_HANDLE hEDGAR2A);
DWORD EDGAR2A_CountCards (DWORD dwVendorID, DWORD dwDeviceID);
BOOL EDGAR2A_IsAddrSpaceActive(EDGAR2A_HANDLE hEDGAR2A,
    EDGAR2A_ADDR addrSpace);

// General read/write function

void EDGAR2A_ReadWriteBlock(EDGAR2A_HANDLE hEDGAR2A,
    EDGAR2A_ADDR addrSpace, DWORD dwOffset, BOOL fRead, PVOID buf,
    DWORD dwBytes, EDGAR2A_MODE mode);
BYTE EDGAR2A_ReadByte (EDGAR2A_HANDLE hEDGAR2A,
    EDGAR2A_ADDR addrSpace, DWORD dwOffset);
WORD EDGAR2A_ReadWord (EDGAR2A_HANDLE hEDGAR2A, EDGAR2A_ADDR addrSpace,
    DWORD dwOffset);
DWORD EDGAR2A_ReadDword (EDGAR2A_HANDLE hEDGAR2A,
    EDGAR2A_ADDR addrSpace, DWORD dwOffset);
void EDGAR2A_WriteByte (EDGAR2A_HANDLE hEDGAR2A, EDGAR2A_ADDR addrSpace,
    DWORD dwOffset, BYTE data);
void EDGAR2A_WriteWord (EDGAR2A_HANDLE hEDGAR2A, EDGAR2A_ADDR addrSpace,
    DWORD dwOffset, WORD data);
void EDGAR2A_WriteDword (EDGAR2A_HANDLE hEDGAR2A, EDGAR2A_ADDR addrSpace,
    DWORD dwOffset, DWORD data);

// FPGAs DONE signals read on bits 3:0
DWORD EDGAR2A_ReadDONE (EDGAR2A_HANDLE hEDGAR2A);

// Reprogram FPGAs writing 1 on bits 3:0
void EDGAR2A_WritenotProgramFpga (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// FPGAs /INIT signals read on bits 3:0
DWORD EDGAR2A_ReadnotINIT (EDGAR2A_HANDLE hEDGAR2A);

// FPGAs RDY/notBUSY read on bits 31,23,15,7
DWORD EDGAR2A_ReadfpgaRdyNotBusy (EDGAR2A_HANDLE hEDGAR2A);

// Set/Reset Interrupt F/F writing 0/1 on bit 7
void EDGAR2A_WriteinterruptRequest (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGA 1 (bits 15:8)
void EDGAR2A_Writecfg_1 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGA 0 (bits 7:0)
void EDGAR2A_Writecfg_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGA 2 (bits 23:16)
void EDGAR2A_Writecfg_2 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGA 3 (bits 31:24)
void EDGAR2A_Writecfg_3 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 1 + 0 (bits 15:0)
void EDGAR2A_Writecfg_1_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 2 + 0  (bits 23:16  ,  7:0)
void EDGAR2A_Writecfg_2_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 0  (bits 31:24  ,  7:0)
void EDGAR2A_Writecfg_3_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 1  (bits 31:24  ,  15:8)
void EDGAR2A_Writecfg_3_1 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 2  (bits 31:16)
void EDGAR2A_Writecfg_3_2 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 2 + 1 + 0  (bits 23:0)
void EDGAR2A_Writecfg_2_1_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 2 + 0  (bits 31:16 , 7:0)
void EDGAR2A_Writecfg_3_2_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 1 + 0  (bits 31:8)
void EDGAR2A_Writecfg_3_2_1 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 2 + 1 + 0  (bits 31:0)
void EDGAR2A_Writecfg_3_2_1_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 3 + 1 + 0  (bits 31:24 , 15:0)
void EDGAR2A_Writecfg_3_1_0 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Configure FPGAs 2 + 1  (bits 23:8)
void EDGAR2A_Writecfg_2_1 (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Enable/Disable CPLD Generated PCI Control Signals
void EDGAR2A_WriteenablePciCtlSignals (EDGAR2A_HANDLE hEDGAR2A,DWORD data);

// Program JTAG Daisy-Chain Structure
void EDGAR2A_WriteprogramJtagChain (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Select Secondary Clock - SCLOCK
void EDGAR2A_WriteSCLOCK (EDGAR2A_HANDLE hEDGAR2A, DWORD data);

// Handle interrupts
BOOL EDGAR2A_IntIsEnabled (EDGAR2A_HANDLE hEDGAR2A);
BOOL EDGAR2A_IntEnable (EDGAR2A_HANDLE hEDGAR2A,
    EDGAR2A_INT_HANDLER funcIntHandler);
void EDGAR2A_IntDisable (EDGAR2A_HANDLE hEDGAR2A);

// Access to PCI configuration registers
void EDGAR2A_WritePCIReg(EDGAR2A_HANDLE hEDGAR2A,
    DWORD dwReg, DWORD dwData);
DWORD EDGAR2A_ReadPCIReg(EDGAR2A_HANDLE hEDGAR2A, DWORD dwReg);

// This string is set to an error message, if one occurs
extern CHAR EDGAR2A_ErrorString[];

// Program FPGAs on EDgAR-2

int programarFpga0  ( EDGAR2A_HANDLE );
int programarFpga1  ( EDGAR2A_HANDLE );
int programarFpga2  ( EDGAR2A_HANDLE );
int programarFpga3  ( EDGAR2A_HANDLE );
int programar4Fpgas ( EDGAR2A_HANDLE , char *);

#ifdef __cplusplus
}
#endif

#endif