-- ----------------------------------------------------------------------- -- FILE: DESmedium_synth0.vhd -- DATE: 12 December 2000 -- AUTHOR: Antonio Esteves, GEC-DI-UM -- -- DES algorithm pipelined in 4 stages (stage 0 or HW1 partition). -- Synthesizable version. -- ----------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.DESlib.all; entity DESpartition0 is PORT ( NOTWR : in std_logic ; NOTRD : in std_logic ; RESET : in std_logic ; PCLOCK : in std_logic ; SCLOCK : in std_logic ; BASE_HIT0 : in std_logic ; ADDR_VLD : in std_logic ; S_DATA_VLD : in std_logic ; PCI_CMD7 : in std_logic ; PCI_CMD6 : in std_logic ; S_CBE : in std_logic ; ADDR : in std_logic_vector(17 downto 0) ; DATA : inout std_logic_vector( 7 downto 0) ; S_SRC_EN : in std_logic ; S_DATA : in std_logic ; RSTOUTVALIDS_UP : out std_logic ; ADD_UP : out std_logic_vector(2 downto 0) ; NOTRD_UP : out std_logic ; DATA_UP : in std_logic_vector(27 downto 0) ; DATA_DWN : out std_logic_vector(27 downto 0) ; NOTRD_DWN : in std_logic ; ADD_DWN : in std_logic_vector(2 downto 0) ; RSTOUTVALIDS_DWN : in std_logic ; CONNECTOR : inout std_logic_vector(15 downto 0) ; DATA2CPLD : inout std_logic_vector( 7 downto 0) ; CLK_CPLD : in std_logic_vector( 1 downto 0) ; CLK_DWN_OUT : out std_logic ; CLK_DWN_IN : in std_logic ; CLK_UP_OUT : out std_logic ; CLK_UP_IN : in std_logic ; GENERICO : inout std_logic_vector( 2 downto 1) ) ; end DESpartition0; ARCHITECTURE structural OF DESpartition0 IS component fpga_interface port ( -- Signals connecting the FPGA to the exterior NOTWR : in std_logic ; NOTRD : in std_logic ; RESET : in std_logic ; PCLOCK : in std_logic ; SCLOCK : in std_logic ; BASE_HIT0 : in std_logic ; ADDR_VLD : in std_logic ; S_DATA_VLD : in std_logic ; PCI_CMD7 : in std_logic ; PCI_CMD6 : in std_logic ; S_CBE : in std_logic ; ADDR : in std_logic_vector(17 downto 0) ; DATA : inout std_logic_vector( 7 downto 0) ; S_SRC_EN : in std_logic ; S_DATA : in std_logic ; RSTOUTVALIDS_UP : out std_logic ; ADD_UP : out std_logic_vector(2 downto 0) ; NOTRD_UP : out std_logic ; DATA_UP : in std_logic_vector(27 downto 0) ; DATA_DWN : out std_logic_vector(27 downto 0) ; NOTRD_DWN : in std_logic ; ADD_DWN : in std_logic_vector(2 downto 0) ; RSTOUTVALIDS_DWN : in std_logic ; CONNECTOR : inout std_logic_vector(15 downto 0) ; DATA2CPLD : inout std_logic_vector( 7 downto 0) ; CLK_CPLD : in std_logic_vector( 1 downto 0) ; CLK_DWN_OUT : out std_logic ; CLK_DWN_IN : in std_logic ; CLK_UP_OUT : out std_logic ; CLK_UP_IN : in std_logic ; GENERICO : inout std_logic_vector( 2 downto 1); -- Signals connecting to the rest of the FPGA logic NOTWR_I : out std_logic ; NOTRD_I : out std_logic ; RESET_I : out std_logic ; PCLOCK_I : out std_logic ; SCLOCK_I : out std_logic ; BASE_HIT0_I : out std_logic ; ADDR_VLD_I : out std_logic ; S_DATA_VLD_I : out std_logic ; PCI_CMD7_I : out std_logic ; PCI_CMD6_I : out std_logic ; S_CBE_I : out std_logic ; ADDR_I : out std_logic_vector(17 downto 0) ; DATA_I : out std_logic_vector( 7 downto 0) ; DATA_O : in std_logic_vector( 7 downto 0) ; S_SRC_EN_I : out std_logic ; S_DATA_I : out std_logic ; RSTprevOutValids : in std_logic ; addReads : in std_logic_vector(2 downto 0) ; notRDprevStage : in std_logic ; DATA_UP_I : out std_logic_vector(27 downto 0) ; CONNECTOR_O : in std_logic_vector(15 downto 0) ; CONNECTOR_I : out std_logic_vector(15 downto 0) ; DATA_DWN_O : in std_logic_vector(27 downto 0) ; notRDinDwn : out std_logic ; addInDwn : out std_logic_vector(2 downto 0) ; RSToutValids : out std_logic ; DATA2CPLD_O : in std_logic_vector( 7 downto 0) ; DATA2CPLD_I : out std_logic_vector( 7 downto 0) ; CLK_CPLD_I : out std_logic_vector( 1 downto 0) ; CLK_DWN_OUT_O : in std_logic ; CLK_DWN_IN_I : out std_logic ; CLK_UP_OUT_O : in std_logic ; CLK_UP_IN_I : out std_logic ; GENERICO_O : in std_logic_vector( 2 downto 1) ; GENERICO_I : out std_logic_vector( 2 downto 1) ; -- Signals to control tri-state buffers on bi-direccional pins not_oe_d : in std_logic; not_oe_d2c : in std_logic; not_oe_gen : in std_logic; not_oe_conn : in std_logic ); end component ; component ctl_fpga_interface port ( NOTWR_I : in std_logic ; NOTRD_I : in std_logic ; RESET_I : in std_logic ; PCLOCK_I : in std_logic ; BASE_HIT0_I : in std_logic ; ADDR_VLD_I : in std_logic ; S_DATA_VLD_I : in std_logic ; PCI_CMD7_I : in std_logic ; PCI_CMD6_I : in std_logic ; ADDR_I : in std_logic_vector(17 downto 0) ; S_DATA_I : in std_logic ; notOEdoutB0 : out STD_LOGIC; notOEdoutB1 : out STD_LOGIC; notOEdoutB2 : out STD_LOGIC; notOEdoutB3 : out STD_LOGIC; notOEdoutB4 : out STD_LOGIC; notOEdoutB5 : out STD_LOGIC; notOEdoutB6 : out STD_LOGIC; notOEdoutB7 : out STD_LOGIC; notOEreadNewData : out STD_LOGIC; notOEwriteData : out STD_LOGIC; LOADdinB0 : out STD_LOGIC; LOADdinB1 : out STD_LOGIC; LOADdinB2 : out STD_LOGIC; LOADdinB3 : out STD_LOGIC; LOADdinB4 : out STD_LOGIC; LOADdinB5 : out STD_LOGIC; LOADdinB6 : out STD_LOGIC; LOADdinB7 : out STD_LOGIC; LOADkeyInB0 : out STD_LOGIC; LOADkeyInB1 : out STD_LOGIC; LOADkeyInB2 : out STD_LOGIC; LOADkeyInB3 : out STD_LOGIC; LOADkeyInB4 : out STD_LOGIC; LOADkeyInB5 : out STD_LOGIC; LOADkeyInB6 : out STD_LOGIC; LOADkeyInB7 : out STD_LOGIC; LOADdinValid : out STD_LOGIC; LOADencryptIn : out STD_LOGIC; LOADwriteDone : out STD_LOGIC; LOADresetFf : out STD_LOGIC; LOADstartFsm : out STD_LOGIC ); end component; component fsm0 is port ( clk : in STD_LOGIC; resetFf : in STD_LOGIC; startFsm : in STD_LOGIC; newData : in STD_LOGIC; selectIn : in STD_LOGIC; selectOut : in STD_LOGIC; stage : in STD_LOGIC_VECTOR (1 downto 0); round : in STD_LOGIC_VECTOR (3 downto 0); writeDone : in STD_LOGIC; dinValidMux : in STD_LOGIC; countingReads : in STD_LOGIC; doutValidR : in STD_LOGIC; notFirstTime : in std_logic; CEipPc1 : out STD_LOGIC; CEmuxedIn : out STD_LOGIC; CEdesEp : out STD_LOGIC; CEdesSbox : out STD_LOGIC; CEoutputsR : out STD_LOGIC; CEround : out STD_LOGIC; CEoutputs : out STD_LOGIC; CEwriteData : out STD_LOGIC; CEreadNewData : out STD_LOGIC; CEreadPrevStage : out STD_LOGIC; CEoutputValid : out STD_LOGIC; RSTreadNewData : out STD_LOGIC; RSTreadPrevStage : out STD_LOGIC; RSTwriteDone : out STD_LOGIC; RSTwriteData : out STD_LOGIC; RSTdinValids : out STD_LOGIC; RSTprevOutValids : out STD_LOGIC; RSTnewData : out STD_LOGIC; notRDprevStage : out STD_LOGIC; LOADcntReads : out STD_LOGIC; CLKcntReads : out STD_LOGIC; LOADenable : out STD_LOGIC; LOADdinValidR : out sTD_LOGIC ); end component; component ffd_ce is port ( data_in : in std_logic; clock : in std_logic; enable : in std_logic; data_out : out std_logic ); end component; component ffd_ce_rst is port ( data_in : in std_logic; clock : in std_logic; enable : in std_logic; reset : in std_logic; data_out : out std_logic ); end component; component counterDown is generic (w: NATURAL); port ( start : in std_logic_vector (w-1 downto 0); c : in std_logic; load : in std_logic; reset : in std_logic; count : inout std_logic_vector (w-1 downto 0); counting : inout std_logic ); end component; component registerD_ce IS generic(w: NATURAL); PORT( data_in : in std_logic_vector(w-1 downto 0); clock : in std_logic; enable : in std_logic; data_out : out std_logic_vector(w-1 downto 0) ) ; end component; component registerD_ce_rst IS generic(w: NATURAL); PORT( data_in : in std_logic_vector(w-1 downto 0); clock : in std_logic; enable : in std_logic; reset : in std_logic; data_out : out std_logic_vector(w-1 downto 0) ) ; end component; -- -------------------------------------------------------------- -- Signals connecting the FPGA PADs to the rest of the FPGA logic -- -------------------------------------------------------------- signal NOTWR_I : std_logic ; signal NOTRD_I : std_logic ; signal RESET_I : std_logic ; signal PCLOCK_I : std_logic ; signal SCLOCK_I : std_logic ; signal BASE_HIT0_I : std_logic ; signal ADDR_VLD_I : std_logic ; signal S_DATA_VLD_I : std_logic ; signal PCI_CMD7_I : std_logic ; signal PCI_CMD6_I : std_logic ; signal S_CBE_I : std_logic ; signal ADDR_I : std_logic_vector(17 downto 0) ; signal DATA_I : std_logic_vector( 7 downto 0) ; signal DATA_O : std_logic_vector( 7 downto 0) ; signal S_SRC_EN_I : std_logic ; signal S_DATA_I : std_logic ; signal addReads : std_logic_vector( 2 downto 0) ; signal DATA_UP_I : std_logic_vector(27 downto 0) ; signal RSToutValids : std_logic ; signal DATA_DWN_O : std_logic_vector(27 downto 0) ; signal notRDinDwn : std_logic ; signal addInDwn : std_logic_vector(2 downto 0) ; -- ----------------------------------------------------------- -- Signals to control tri-state buffers on bi-direccional pads -- ----------------------------------------------------------- signal notOEd : std_logic; -- -------------------------------------------------------------- -- FSM outputs -- -------------------------------------------------------------- signal CEipPc1 : STD_LOGIC; signal CEmuxedIn : STD_LOGIC; signal CEdesEp : STD_LOGIC; signal CEdesSbox : STD_LOGIC; signal CEoutputsR : STD_LOGIC; signal CEround : STD_LOGIC; signal CEoutputs : STD_LOGIC; signal CEwriteData : STD_LOGIC; signal CEreadNewData : STD_LOGIC; signal CEreadPrevStage : STD_LOGIC; signal CEoutputValid : STD_LOGIC; signal RSTreadNewData : STD_LOGIC; signal RSTreadPrevStage : STD_LOGIC; signal RSTwriteDone : STD_LOGIC; signal RSTwriteData : STD_LOGIC; signal RSTdinValids : STD_LOGIC; signal RSTprevOutValids : STD_LOGIC; signal RSTnewData : STD_LOGIC; signal notRDprevStage : STD_LOGIC; signal LOADcntReads : STD_LOGIC; signal CLKcntReads : STD_LOGIC; signal LOADenable : STD_LOGIC; signal LOADdinValidR : STD_LOGIC; -- -------------------------------------------------------------- -- FSM inputs -- -------------------------------------------------------------- signal clk : STD_LOGIC; signal resetFf : STD_LOGIC; signal startFsm : STD_LOGIC; signal newData : STD_LOGIC; signal writeDone : STD_LOGIC; signal countingReads : STD_LOGIC; -- ------------------------------------------------------------------- -- notOE (LOAD) signals used to read (write) from (to) the FPGA -- through the PCI bus -- ------------------------------------------------------------------- signal notOEdoutB0 : STD_LOGIC; signal notOEdoutB1 : STD_LOGIC; signal notOEdoutB2 : STD_LOGIC; signal notOEdoutB3 : STD_LOGIC; signal notOEdoutB4 : STD_LOGIC; signal notOEdoutB5 : STD_LOGIC; signal notOEdoutB6 : STD_LOGIC; signal notOEdoutB7 : STD_LOGIC; signal notOEreadNewData : STD_LOGIC; signal notOEwriteData : STD_LOGIC; signal LOADdinB0 : STD_LOGIC; signal LOADdinB1 : STD_LOGIC; signal LOADdinB2 : STD_LOGIC; signal LOADdinB3 : STD_LOGIC; signal LOADdinB4 : STD_LOGIC; signal LOADdinB5 : STD_LOGIC; signal LOADdinB6 : STD_LOGIC; signal LOADdinB7 : STD_LOGIC; signal LOADkeyInB0 : STD_LOGIC; signal LOADkeyInB1 : STD_LOGIC; signal LOADkeyInB2 : STD_LOGIC; signal LOADkeyInB3 : STD_LOGIC; signal LOADkeyInB4 : STD_LOGIC; signal LOADkeyInB5 : STD_LOGIC; signal LOADkeyInB6 : STD_LOGIC; signal LOADkeyInB7 : STD_LOGIC; signal LOADdinValid : STD_LOGIC; signal LOADencryptIn : STD_LOGIC; signal LOADwriteDone : STD_LOGIC; signal LOADresetFf : STD_LOGIC; signal LOADstartFsm : STD_LOGIC; -- ------------------------------------------------------------------- -- notOE signals that allow next FPGA (stage) to read local registers -- through the DATA_DWN(32:0) connection -- ------------------------------------------------------------------- signal notOEdoutValidR : std_logic; signal notOEencryptOutR : std_logic; signal notOEdoutRls : std_logic; signal notOEdoutRmed : std_logic; signal notOEdoutRms : std_logic; signal notOEkeyOutRls : std_logic; signal notOEkeyOutRms : std_logic; -- ------------------------------------------------------------------- -- LOAD signals that allow values read from previous FPGA (stage), -- through the DATA_UP(32:0) connection, to be stored in local registers -- ------------------------------------------------------------------- signal LOADkeyInRms : std_logic; signal LOADkeyInRls : std_logic; signal LOADdinRms : std_logic; signal LOADdinRmed : std_logic; signal LOADdinRls : std_logic; signal LOADencryptInR : std_logic; -- ------------------------------------------------------------------- -- DES registered signals -- ------------------------------------------------------------------- signal doutIp : std_logic_vector (63 downto 0) ; signal keyOutPc1 : std_logic_vector (55 downto 0) ; signal dataEp : std_logic_vector (47 downto 0) ; signal encryptOut : std_logic; signal dout : std_logic_vector (63 downto 0) ; signal din : std_logic_vector (63 downto 0) ; signal keyIn : std_logic_vector (63 downto 0) ; signal dinValid : std_logic; signal encryptIn : std_logic; signal dinR : std_logic_vector (63 downto 0) ; signal keyInR : std_logic_vector (55 downto 0) ; signal dinValidR : std_logic; signal encryptInR : std_logic; signal doutR : std_logic_vector (63 downto 0) ; signal keyOutR : std_logic_vector (55 downto 0) ; signal doutValidR : std_logic; signal encryptOutR : std_logic; -- equal to "encryptOut" signal writeData : std_logic; signal readNewData : STD_LOGIC; signal readPrevStage : std_logic; -- ------------------------------------------------------------------- -- DES interconnection signals -- ------------------------------------------------------------------- signal desIpOut : std_logic_vector (63 downto 0); signal desPc1Out : std_logic_vector (55 downto 0); signal dinValidMux : std_logic; signal dinMux : std_logic_vector (63 downto 0); signal keyInMux : std_logic_vector (55 downto 0); signal encryptMux : std_logic; signal desEpXored : std_logic_vector (47 downto 0); signal dataSbox : std_logic_vector (31 downto 0); signal DESpboxXored : std_logic_vector (31 downto 0); signal keyShiftedMux : std_logic_vector (55 downto 0); signal pc2Key : std_logic_vector (47 downto 0); signal dValid : std_logic; signal doutRin : std_logic_vector (63 downto 0); signal doutValid : std_logic; signal encryptShift : std_logic_vector (4 downto 0) ; signal encryptShiftR1 : std_logic_vector (4 downto 0) ; signal encryptShiftR2 : std_logic_vector (4 downto 0) ; signal encryptShiftR3 : std_logic_vector (4 downto 0) ; signal encryptShiftR4 : std_logic_vector (4 downto 0) ; signal decryptShift : std_logic_vector (4 downto 0) ; signal decryptShiftR1 : std_logic_vector (4 downto 0) ; signal decryptShiftR2 : std_logic_vector (4 downto 0) ; signal decryptShiftR3 : std_logic_vector (4 downto 0) ; signal decryptShiftR4 : std_logic_vector (4 downto 0) ; -- ------------------------------------------------------------------- -- DES auxiliary signals -- ------------------------------------------------------------------- signal sig_gnd, sig_vcc : std_logic; signal sig_vcc3 : std_logic_vector (2 downto 0); signal selectIn : std_logic; signal selectOut : std_logic; signal clkFirstTime : std_logic; signal notFirstTime : std_logic; signal round : std_logic_vector (3 downto 0) ; signal stage : std_logic_vector (1 downto 0) ; signal RSToutputsValid : std_logic; signal resetStartFsm : std_logic; signal resetStart : std_logic; begin ----------------------------------------------------------------- -- ----------------------------------------------------------------- clk <= PCLOCK_I ; notOEd <= notOEdoutB0 and notOEdoutB1 and notOEdoutB2 and notOEdoutB3 and notOEdoutB4 and notOEdoutB5 and notOEdoutB6 and notOEdoutB7 and notOEreadNewData and notOEwriteData; notOEd2c <= '1' ; -- (if DATA2CPLD[] pins are used CHANGE this) notOEdup <= '1' ; -- (if DATA_UP[] pins are used CHANGE this) notOEddwn <= '1' ; -- (if DATA_DWN[] pins are used CHANGE this) notOEgen <= '1' ; -- (if GENERICO[] pins are used CHANGE this) notOEconn <= '1' ; -- (if CONNECTOR[] pins are used CHANGE this) ----------------------------------------------------------------- -- Fixed Parameters ----------------------------------------------------------------- sig_gnd <= '0' ; sig_vcc <= '1' ; sig_vcc3 <= "111" ; stage <= "00" ; ----------------------------------------------------------------- -- ----------------------------------------------------------------- selectIn <= round(3) or round(2); selectOut <= (( ( (not round(3)) and (not round(2))) and ((not round(1)) or (not round(0))) ) or (round(3) and round(2) and round(1) and round(0))) and notFirstTime; clkFirstTime <= round(3); resetStart <= resetFf or startFsm; encryptOutR <= encryptOut; LOADkeyInRms <= LOADenable and (not addReads(2)) and (not addReads(1)) and addReads(0) ; LOADkeyInRls <= LOADenable and (not addReads(2)) and addReads(1) and (not addReads(0)); LOADdinRms <= LOADenable and (not addReads(2)) and addReads(1) and addReads(0) ; LOADdinRmed <= LOADenable and addReads(2) and (not addReads(1)) and (not addReads(0)); LOADdinRls <= LOADenable and addReads(2) and (not addReads(1)) and addReads(0) ; LOADencryptInR <= LOADenable and addReads(2) and addReads(1) and (not addReads(0)); notOEdoutValidR <= notRDinDwn or (not addInDwn(2)) or (not addInDwn(1)) or (not addInDwn(0)) ; notOEencryptOutR <= notRDinDwn or (not addInDwn(2)) or (not addInDwn(1)) or ( addInDwn(0)) ; notOEdoutRls <= notRDinDwn or (not addInDwn(2)) or ( addInDwn(1)) or (not addInDwn(0)) ; notOEdoutRmed <= notRDinDwn or (not addInDwn(2)) or ( addInDwn(1)) or ( addInDwn(0)) ; notOEdoutRms <= notRDinDwn or ( addInDwn(2)) or (not addInDwn(1)) or (not addInDwn(0)) ; notOEkeyOutRls <= notRDinDwn or ( addInDwn(2)) or (not addInDwn(1)) or ( addInDwn(0)) ; notOEkeyOutRms <= notRDinDwn or ( addInDwn(2)) or ( addInDwn(1)) or (not addInDwn(0)) ; ----------------------------------------------------------------- -- Generation of "notFirstTime" signal ----------------------------------------------------------------- process (resetStart, clkFirstTime) begin if (resetStart = '1') then notFirstTime <= '0'; elsif (clkFirstTime'event and clkFirstTime='1') then notFirstTime <= sig_vcc ; end if; end process; ------------------- -- resetFf F/F -- ------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_I(0) -- Qout: resetFf -- CLOCK: clk -- CE: LOADresetFf RST_FF: ffd_ce port map ( data_in => DATA_I(0) , clock => clk , enable => LOADresetFf , data_out => resetFf ); ------------------- -- startFsm F/F -- ------------------- -- -- RESET: resetFf OR RSTdinValids -- SET: --- -- Din: DATA_I(0) -- Qout: startFsm -- CLOCK: clk -- CE: LOADstartsm resetStartFsm <= resetFf or RSTdinValids; SFSM_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => LOADstartFsm , reset => resetStartFsm , data_out => startFsm ); ---------------------- -- F/F readNewData -- ---------------------- -- -- RESET: RSTreadNewData -- SET: --- -- Din: '1' -- Qout: readNewData -- CLOCK: clk -- CE: CEreadNewData RNEWD_FF: ffd_ce_rst port map ( data_in => sig_vcc , clock => clk , enable => CEreadNewData , reset => RSTreadNewData , data_out => readNewData ); -- connect F/F to the PCI data bus process(notOEreadNewData, readNewData) begin if (notOEreadNewData = '0') then DATA_O(0) <= readNewData ; else DATA_O(0) <= 'Z' ; end if ; end process; ---------------------- -- F/F newData -- ---------------------- -- -- RESET: RSTnewData -- SET: --- -- Din: '1' -- Qout: newData -- CLOCK: clk -- CE: CEreadNewData NEWD_FF: ffd_ce_rst port map ( data_in => sig_vcc , clock => clk , enable => CEreadNewData , reset => RSTnewData , data_out => newData ); ---------------------- -- F/F writeData -- ---------------------- -- -- RESET: RSTwriteData -- SET: --- -- Din: '1' -- Qout: writeData -- CLOCK: clk -- CE: CEwriteData WDATA_FF: ffd_ce_rst port map ( data_in => sig_vcc , clock => clk , enable => CEwriteData , reset => RSTwriteData , data_out => writeData ); -- connect F/F to the PCI data bus process(notOEwriteData, writeData) begin if (notOEwriteData = '0') then DATA_O(0) <= writeData ; else DATA_O(0) <= 'Z' ; end if ; end process; -------------------- -- writeDone F/F -- -------------------- -- -- RESET: RSTwriteDone -- SET: --- -- Din: DATA_I(0) -- Qout: writeDone -- CLOCK: clk -- CE: LOADwriteDone WDONE_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => LOADwriteDone , reset => RSTwriteDone , data_out => writeDone ); -------------------- -- din F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_I(7 downto 0), ... , DATA_I(7 downto 0) -- Qout: din(63 downto 56), ... , din(7 downto 0) -- CLOCK: clk -- CE: LOADdinB7, ... , LOADdinB0 DINB7_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB7 , data_out => din(63 downto 56) ); DINB6_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB6 , data_out => din(55 downto 48) ); DINB5_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB5 , data_out => din(47 downto 40) ); DINB4_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB4 , data_out => din(39 downto 32) ); DINB3_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB3 , data_out => din(31 downto 24) ); DINB2_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB2 , data_out => din(23 downto 16) ); DINB1_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB1 , data_out => din(15 downto 8) ); DINB0_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADdinB0 , data_out => din(7 downto 0) ); -------------------- -- keyIn F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_I(7 downto 0), ... , DATA_I(7 downto 0) -- Qout: keyIn(63 downto 56), ... , keyIn(7 downto 0) -- CLOCK: clk -- CE: LOADkeyInB7, ... , LOADkeyInB0 KINB7_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB7 , data_out => keyIn(63 downto 56) ); KINB6_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB6 , data_out => keyIn(55 downto 48) ); KINB5_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB5 , data_out => keyIn(47 downto 40) ); KINB4_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB4 , data_out => keyIn(39 downto 32) ); KINB3_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB3 , data_out => keyIn(31 downto 24) ); KINB2_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB2 , data_out => keyIn(23 downto 16) ); KINB1_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB1 , data_out => keyIn(15 downto 8) ); KINB0_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_I , clock => clk , enable => LOADkeyInB0 , data_out => keyIn(7 downto 0) ); -------------------- -- dinValid F/F -- -------------------- -- -- RESET: RSTdinvalids -- SET: --- -- Din: DATA_I(0) -- Qout: dinValid -- CLOCK: clk -- CE: LOADdinValid DINV_FF: ffd_ce_rst port map ( data_in => DATA_I(0) , clock => clk , enable => LOADdinValid , reset => RSTdinValids , data_out => dinValid ); -------------------- -- encryptIn F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_I(0) -- Qout: encryptIn -- CLOCK: clk -- CE: LOADencryptIn ENCRYPIN_FF: ffd_ce port map ( data_in => DATA_I(0) , clock => clk , enable => LOADencryptIn , data_out => encryptIn ); ------------------------- -- readPrevStage F/F -- ------------------------- -- -- RESET: RSTreadPrevStage -- SET: --- -- Din: '1' -- Qout: readPrevStage -- CLOCK: clk -- CE: CEreadPrevStage R_PREV_STG_FF: ffd_ce_rst port map ( data_in => sig_vcc , clock => clk , enable => CEreadPrevStage , reset => RSTreadPrevStage , data_out => readPrevStage ); --------------------- -- doutValidR F/F -- --------------------- -- -- RESET: RSToutputsValid -- SET: --- -- Din: '1' -- Qout: doutValidR -- CLOCK: clk -- CE: CEoutputValid RSToutputsValid <= RSToutValids or resetStart; DOUTVAL_FF: ffd_ce_rst port map ( data_in => sig_vcc , clock => clk , enable => CEoutputValid , reset => RSToutputsValid , data_out => doutValidR ); -- connect "doutValidR" to DATA_DWN_O(0) process(notOEdoutValidR, doutValidR) begin if (notOEdoutValidR = '0') then DATA_DWN_O(0) <= doutValidR ; else DATA_DWN_O(0) <= 'Z' ; end if ; end process; --------------------------------- -- encryptOut/encryptOutR F/F -- --------------------------------- -- -- RESET: --- -- SET: --- -- Din: encryptMux -- Qout: encryptOut -- CLOCK: clk -- CE: CEoutputsR ENCRYPT_OUT_FF: ffd_ce port map ( data_in => encryptMux , clock => clk , enable => CEoutputsR , data_out => encryptOut ); -- connect "encryptOutR" to DATA_DWN_O(0) process(notOEencryptOutR, encryptOutR) begin if (notOEencryptOutR = '0') then DATA_DWN_O(0) <= encryptOutR ; else DATA_DWN_O(0) <= 'Z' ; end if ; end process; -------------------- -- doutIp F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: desIpOut -- Qout: doutIp -- CLOCK: clk -- CE: CEipPc1 DOUT_IP_FF: registerD_ce generic map (w => 64) port map ( data_in => desIpOut , clock => clk , enable => CEipPc1 , data_out => doutIp ); -------------------- -- keyOutPc1 F/F -- -------------------- -- -- RESET: RST -- SET: --- -- Din: desPc1Out -- Qout: keyOutPc1 -- CLOCK: clk -- CE: CE KOUT_PC1_FF: registerD_ce generic map (w => 56) port map ( data_in => desPc1Out , clock => clk , enable => CEipPc1 , data_out => keyOutPc1 ); -------------------- -- dataEp F/F -- -------------------- -- -- RESET: RST -- SET: --- -- Din: desEpXored -- Qout: dataEp -- CLOCK: clk -- CE: CEdesEp DATA_EP_FF: registerD_ce generic map (w => 48) port map ( data_in => desEpXored , clock => clk , enable => CEdesEp , data_out => dataEp ); -------------------- -- doutR F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: doutRin -- Qout: doutR -- CLOCK: clk -- CE: CEoutputsR DOUTR_FF: registerD_ce generic map (w => 64) port map ( data_in => doutRin , clock => clk , enable => CEoutputsR , data_out => doutR ); -- connect doutR(27:0) to DATA_DWN_O(27:0) process(notOEdoutRls, doutR) begin if (notOEdoutRls = '0') then DATA_DWN_O(27 downto 0) <= doutR(27 downto 0) ; else DATA_DWN_O(27 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; end if ; end process; -- connect doutR(55:28) to DATA_DWN_O(27:0) process(notOEdoutRmed, doutR) begin if (notOEdoutRmed = '0') then DATA_DWN_O(27 downto 0) <= doutR(55 downto 28) ; else DATA_DWN_O(27 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; end if ; end process; -- connect doutR(63:56) to DATA_DWN_O(7:0) process(notOEdoutRms, doutR) begin if (notOEdoutRms = '0') then DATA_DWN_O(7 downto 0) <= doutR(63 downto 56) ; else DATA_DWN_O(7 downto 0) <= "ZZZZZZZZ" ; end if ; end process; ---------------------- -- keyOutR F/F -- ---------------------- -- -- RESET: --- -- SET: --- -- Din: keyShiftedMux -- Qout: keyOutR -- CLOCK: clk -- CE: CEoutputsR KEY_SHIFT_FF: registerD_ce generic map (w => 56) port map ( data_in => keyShiftedMux , clock => clk , enable => CEoutputsR , data_out => keyOutR ); -- connect keyOutR(27:0) to DATA_DWN_O(27:0) process(notOEkeyOutRls, keyOutR) begin if (notOEkeyOutRls = '0') then DATA_DWN_O(27 downto 0) <= keyOutR (27 downto 0); else DATA_DWN_O(27 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; end if ; end process; -- connect keyOutR(55:28) to DATA_DWN_O(27:0) process(notOEkeyOutRms, keyOutR) begin if (notOEkeyOutRms = '0') then DATA_DWN_O(27 downto 0) <= keyOutR (55 downto 28); else DATA_DWN_O(27 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ; end if ; end process; -------------------- -- dinR F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_UP_I(7 downto 0), DATA_UP_I(27 downto 0), DATA_UP_I(27 downto 0) -- Qout: dinR(63 downto 56) , dinR(55 downto 28) , dinR(27 downto 0) -- CLOCK: clk -- CE: LOADdinRms , LOADdinRmed , LOADdinRls DINR_H_FF: registerD_ce generic map (w => 8) port map ( data_in => DATA_UP_I(7 downto 0) , clock => clk , enable => LOADdinRms , data_out => dinR(63 downto 56) ); DINR_M_FF: registerD_ce generic map (w => 28) port map ( data_in => DATA_UP_I(27 downto 0) , clock => clk , enable => LOADdinRmed , data_out => dinR(55 downto 28) ); DINR_L_FF: registerD_ce generic map (w => 28) port map ( data_in => DATA_UP_I(27 downto 0) , clock => clk , enable => LOADdinRls , data_out => dinR(27 downto 0) ); -------------------- -- keyInR F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_UP_I(27 downto 0) , DATA_UP_I(27 downto 0) -- Qout: keyInR(55 downto 28) , keyInR(27 downto 0) -- CLOCK: clk -- CE: LOADkeyInRms , LOADkeyInRls KINR_H_FF: registerD_ce generic map (w => 28) port map ( data_in => DATA_UP_I(27 downto 0) , clock => clk , enable => LOADkeyInRms , data_out => keyInR(55 downto 28) ); KINR_L_FF: registerD_ce generic map (w => 28) port map ( data_in => DATA_UP_I(27 downto 0) , clock => clk , enable => LOADkeyInRls , data_out => keyInR(27 downto 0) ); -------------------- -- dinValidR F/F -- -------------------- -- -- RESET: RSTdinvalids -- SET: --- -- Din: DATA_UP_I(0) -- Qout: dinValidR -- CLOCK: clk -- CE: LOADdinValidR DINVR_FF: ffd_ce_rst port map ( data_in => DATA_UP_I(0) , clock => clk , enable => LOADdinValidR , reset => RSTdinValids , data_out => dinValidR ); -------------------- -- encryptInR F/F -- -------------------- -- -- RESET: --- -- SET: --- -- Din: DATA_UP_I(0) -- Qout: encryptInR -- CLOCK: clk -- CE: LOADencryptInR ENCRYPINR_FF: ffd_ce port map ( data_in => DATA_UP_I(0) , clock => clk , enable => LOADencryptInR , data_out => encryptInR ); ------------------------------------------------------------ -- nShifts: define number of shifts used to generate keys -- ======= K1 to K16 on round 1 to 16 ------------------------------------------------------------ process (round) -- Shifts for STAGE 1 begin case round is when "0000" | "0001" | "0010" | "0011" => -- shift for round 1 encryptShift <= "00001"; decryptShift <= "00000"; when "0100" | "0101" | "0110" | "0111" => -- shift for round 5 encryptShift <= "00010"; decryptShift <= "00010"; when "1000" | "1001" | "1010" | "1011" => -- shift for round 9 encryptShift <= "00001"; decryptShift <= "00001"; when "1100" | "1101" | "1110" | "1111" => -- shift for round 13 encryptShift <= "00010"; decryptShift <= "00010"; when others => encryptShift <= "00000"; decryptShift <= "00000"; end case; end process; ---------------------------------------------------------------------- -- Muxes for first stage inputs ---------------------------------------------------------------------- process (selectIn, dinValid, dinValidR) -- dinValidMux begin if selectIn='1' then dinValidMux <= dinValidR; -- from previous round else dinValidMux <= dinValid; -- DES input end if; end process; process (selectIn, doutIp, dinR) -- dinMux begin if selectIn='1' then dinMux <= dinR; -- from previous round else dinMux <= doutIp; -- DES input end if; end process; process (selectIn, keyOutPc1, keyInR) -- keyInMux begin if selectIn='1' then keyInMux <= keyInR; -- from previous round else keyInMux <= keyOutPc1; -- DES input end if; end process; process (selectIn, encryptIn, encryptInR) -- encryptMux begin if selectIn='1' then encryptMux <= encryptInR; -- from previous round else encryptMux <= encryptIn; -- DES input end if; end process; ----------------------------------------------------------------- -- desIP: apply initial permutation (IP) -- ===== ----------------------------------------------------------------- desIpOut <= DESip(din); ----------------------------------------------------------------- -- desPC1: apply permuted choice 1 -- ====== (generates a 56-bits key from a 64-bits key) ----------------------------------------------------------------- desPc1Out <= DESpc1 (keyIn); ----------------------------------------------------------------- -- desEP: expand least significant half of the permuted input data -- ===== from 32 to 48 bits and add result with the round key (Ki) ----------------------------------------------------------------- desEpXored <= DESep(dinMux(31 downto 0)) xor pc2Key; ------------------------------------------------------------ -- desSbox: expanded data is replaced by values read from the -- ======= substitution tables ------------------------------------------------------------ dataSbox <= DESsbox(dataEp); ------------------------------------------------------------ -- desPbox: apply permutation P and add result with most -- ======= significant half of the permuted input data ------------------------------------------------------------ DESpboxXored <= DESpbox(dataSbox) xor dinMux(63 downto 32); ------------------------------------------------------------ -- wrDout: aggregate two halves of the current round output data and -- ====== output it; signal next round that current round is completed ------------------------------------------------------------ doutRin <= (dinMux(31 downto 0) & DESpboxXored); ------------------------------------------------------------ -- MUX for left and right shifted KEY ------------------------------------------------------------ process ( keyInMux, encryptMux, encryptShift, decryptShift ) begin if encryptMux='1' then -- keyShiftL -- ========= keyShiftedMux <= DESkeyLshift(keyInMux,encryptShift); else -- keyShiftR -- ========= keyShiftedMux <= DESkeyRshift(keyInMux,decryptShift); end if; end process; ------------------------------------------------------------ -- desPC2: apply permuted choice 2 -- ====== ------------------------------------------------------------ Pc2Key <= DESpc2(keyShiftedMux); ------------------------------------------------------------ -- Generate round "doutValid" ------------------------------------------------------------ process ( round ) begin if ((round(3)='0') and (round(2)='0') and (round(1)='0') and (round(0)='0')) then dValid <= '0'; else dValid <= '1'; end if; end process; ------------------------------------------------------------ -- Generate DES "doutValid" ------------------------------------------------------------ doutValid <= selectOut and doutValidR; ------------------------------------------------------------ -- Counter for current DES round (4-BIT UP COUNTER) -- -- CLOCK: clk -- RESET: resetStart -- OUT: round -- ENABLE: CEround ------------------------------------------------------------ process (clk, resetStart, CEround) begin if resetStart='1' then round <= "0000"; elsif clk'event and clk='1' then if CEround='1' then round <= round + 1; end if; end if; end process; ---------------------------------------------------------------------- -- 3-BIT DOWN COUNTER THAT DEFINES ADDRESS USED ON PREVIOUS STAGE READING -- -- START VALUE: "111" -- CLOCK: CLKcntReads -- LOAD: LOADcntReads -- RESET: resetStart -- COUNT: addReads -- COUNTING: countingReads ---------------------------------------------------------------------- ADDRESS_CNT: counterDown generic map (w => 3) port map ( start => sig_vcc3 , c => CLKcntReads , load => LOADcntReads , reset => resetStart , count => addReads , counting => countingReads ); -- ------------------------------------------------------------------- -- Generation of the notOE (LOAD) signals used to read (write) from -- (to) the FPGA through the PCI bus -- ------------------------------------------------------------------- CTL_INTERF: ctl_fpga_interface port map ( NOTWR_I => NOTWR_I , NOTRD_I => NOTRD_I , RESET_I => RESET_I , PCLOCK_I => PCLOCK_I , BASE_HIT0_I => BASE_HIT0_I , ADDR_VLD_I => ADDR_VLD_I , S_DATA_VLD_I => S_DATA_VLD_I , PCI_CMD7_I => PCI_CMD7_I , PCI_CMD6_I => PCI_CMD6_I , ADDR_I => ADDR_I , S_DATA_I => S_DATA_I , notOEdoutB0 => notOEdoutB0 , notOEdoutB1 => notOEdoutB1 , notOEdoutB2 => notOEdoutB2 , notOEdoutB3 => notOEdoutB3 , notOEdoutB4 => notOEdoutB4 , notOEdoutB5 => notOEdoutB5 , notOEdoutB6 => notOEdoutB6 , notOEdoutB7 => notOEdoutB7 , notOEreadNewData => notOEreadNewData , notOEwriteData => notOEwriteData , LOADdinB0 => LOADdinB0 , LOADdinB1 => LOADdinB1 , LOADdinB2 => LOADdinB2 , LOADdinB3 => LOADdinB3 , LOADdinB4 => LOADdinB4 , LOADdinB5 => LOADdinB5 , LOADdinB6 => LOADdinB6 , LOADdinB7 => LOADdinB7 , LOADkeyInB0 => LOADkeyInB0 , LOADkeyInB1 => LOADkeyInB1 , LOADkeyInB2 => LOADkeyInB2 , LOADkeyInB3 => LOADkeyInB3 , LOADkeyInB4 => LOADkeyInB4 , LOADkeyInB5 => LOADkeyInB5 , LOADkeyInB6 => LOADkeyInB6 , LOADkeyInB7 => LOADkeyInB7 , LOADdinValid => LOADdinValid , LOADencryptIn => LOADencryptIn , LOADwriteDone => LOADwriteDone , LOADresetFf => LOADresetFf , LOADstartFsm => LOADstartFsm ); -- ------------------------------------------------------------------- -- FSM THAT CONTROLS THE EXECUTION OF THE DES ROUND -- ALLOCATED TO EACH FPGA -- ------------------------------------------------------------------- FSM_DES: fsm0 port map ( clk => clk , resetFf => resetFf , startFsm => startFsm , newData => newData , selectIn => selectIn , selectOut => selectOut , stage => stage , round => round , writeDone => writeDone , dinValidMux => dinValidMux , countingReads => countingReads , doutValidR => doutValidR , notFirstTime => notFirstTime , CEipPc1 => CEipPc1 , CEmuxedIn => CEmuxedIn , CEdesEp => CEdesEp , CEdesSbox => CEdesSbox , CEoutputsR => CEoutputsR , CEround => CEround , CEoutputs => CEoutputs , CEwriteData => CEwriteData , CEreadNewData => CEreadNewData , CEreadPrevStage => CEreadPrevStage , CEoutputValid => CEoutputValid , RSTreadNewData => RSTreadNewData , RSTreadPrevStage => RSTreadPrevStage , RSTwriteDone => RSTwriteDone , RSTwriteData => RSTwriteData , RSTdinValids => RSTdinValids , RSTprevOutValids => RSTprevOutValids , RSTnewData => RSTnewData , notRDprevStage => notRDprevStage , LOADcntReads => LOADcntReads , CLKcntReads => CLKcntReads , LOADenable => LOADenable , LOADdinValidR => LOADdinValidR ); -- -------------------------------------------------------------- -- Interface with the module that instantiates the FPGA PADs -- -------------------------------------------------------------- INTERF: fpga_interface port map ( -- Signals connecting the fpga to the exterior NOTWR => NOTWR , NOTRD => NOTRD , RESET => RESET , PCLOCK => PCLOCK , SCLOCK => SCLOCK , BASE_HIT0 => BASE_HIT0 , ADDR_VLD => ADDR_VLD , S_DATA_VLD => S_DATA_VLD , PCI_CMD7 => PCI_CMD7 , PCI_CMD6 => PCI_CMD6 , S_CBE => S_CBE , ADDR => ADDR , DATA => DATA , S_SRC_EN => S_SRC_EN , S_DATA => S_DATA , RSTOUTVALIDS_UP => RSTOUTVALIDS_UP , ADD_UP => ADD_UP , NOTRD_UP => NOTRD_UP , DATA_UP => DATA_UP , DATA_DWN => DATA_DWN , NOTRD_DWN => NOTRD_DWN , ADD_DWN => ADD_DWN , RSTOUTVALIDS_DWN => RSTOUTVALIDS_DWN , CONNECTOR => CONNECTOR , -- (15 downto 0) DATA2CPLD => DATA2CPLD , -- ( 7 downto 0) CLK_CPLD => CLK_CPLD , -- ( 1 downto 0) CLK_DWN_OUT => CLK_DWN_OUT , CLK_DWN_IN => CLK_DWN_IN , CLK_UP_OUT => CLK_UP_OUT , CLK_UP_IN => CLK_UP_IN , GENERICO => GENERICO , -- ( 2 downto 1) -- Signals connecting to the rest of the fpga logic NOTWR_I => NOTWR_I , NOTRD_I => NOTRD_I , RESET_I => RESET_I , PCLOCK_I => PCLOCK_I , SCLOCK_I => SCLOCK_I , BASE_HIT0_I => BASE_HIT0_I , ADDR_VLD_I => ADDR_VLD_I , S_DATA_VLD_I => S_DATA_VLD_I , PCI_CMD7_I => PCI_CMD7_I , PCI_CMD6_I => PCI_CMD6_I , S_CBE_I => S_CBE_I , ADDR_I => ADDR_I , -- (17 downto 0) DATA_I => DATA_I , -- ( 7 downto 0) DATA_O => DATA_O , -- ( 7 downto 0) S_SRC_EN_I => S_SRC_EN_I , S_DATA_I => S_DATA_I , RSTprevOutValids => RSTprevOutValids , addReads => addReads , -- (2 downto 0) notRDprevStage => notRDprevStage , DATA_UP_I => DATA_UP_I , -- (27 downto 0) CONNECTOR_O => CONNECTOR_O , -- (15 downto 0) CONNECTOR_I => CONNECTOR_I , -- (15 downto 0) DATA_DWN_O => DATA_DWN_O , -- (27 downto 0) notRDinDwn => notRDinDwn , addInDwn => addInDwn , -- (2 downto 0) RSToutValids => RSToutValids , DATA2CPLD_O => DATA2CPLD_O , -- ( 7 downto 0) DATA2CPLD_I => DATA2CPLD_I , -- ( 7 downto 0) CLK_CPLD_I => CLK_CPLD_I , -- ( 1 downto 0) CLK_DWN_OUT_O => CLK_DWN_OUT_O , CLK_DWN_IN_I => CLK_DWN_IN_I , CLK_UP_OUT_O => CLK_UP_OUT_O , CLK_UP_IN_I => CLK_UP_IN_I , GENERICO_O => GENERICO_O , -- ( 2 downto 1) GENERICO_I => GENERICO_I , -- ( 2 downto 1) -- Signals to control tri-state buffers of bi-direccional pins not_oe_d => notOEd , not_oe_d2c => notOEd2c , not_oe_gen => notOEgen , not_oe_conn => notOEconn ); end structural ; -- -----------------------------------------------------------------------