EDgAR-2 Board Page
GEC-DI-UMinho
EDgAR-2
An FPGA/CPLD based Machine for Hardware/Software Codesign
and for Rapid System Prototyping
Board Architecture The EDgAR-2 board is the successor of the EDgAR. Both boards were developed at the Informatics Department from the University of Minho. The EDgAR is a PC board, based on programmable devices, and first conceived as part of a stand alone emulation tool for digital systems. It includes several FPGAs (Xilinx 3K) and CPLDs (MACH 210) connected to the address/data busses and that can be manualy interconnected with connecters. After the construction of this first prototype, the advent of In System Programmable (ISP) devices, devices with more logic, and the technological advances of PC architectures, gave us the opportunity to design a new EDgAR (EDgAR-2), exploring the high PCI bus performance, and much more powerful in terms of logic capacity. EDgAR-2 includes two types of programmable logic devices: one based on coarse grain two level logic blocks, with guaranteed time delay (CPLDs), typically used for control paths; the other based on fine grain multi-level logic blocks (FPGAs), typically used for data paths. The architecture of the board is basically a 4-sized array of Control Unit <--> Data Path cells. Each of this cells is implemented with a Xilinx 4013XLT FPGA and a 95108 CPLD. Each cell works with a different byte of the 32 bits data bus. The board includes also the following facilities:The board is operated on a Windows NT system and connected to the main board by mean of the PCI Bus. For this reason, a Target PCI Controller implementing the interface between the EDgAR-2 and PCI bus, is included. This interface uses the Xilinx PCI LogiCORE 2.01 soluction for 0 wait-states. EDgAR-2 offers an interesting low cost environment to research on codesign methodologies and on hardware alternatives for a broad range of time critical problems.
- fully in system programmable via dedicated logic (faster) and JTAG boundary-scan standard;
- clock selection (frequency and source);
- possibility to interrupt the host system;
- facilities to copy blocks of data to/from board to host;
- possibilty to be connected with one/two other identical board(s), building a pipeline.
Simplified Block Diagram
Picture of EDgAR-2 (click on it to zoom in)
Copyright © 1999, António J A Esteves, All Rights Reserved Last modified: 19 Nov 1999